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Expose x86 XCR0 register #2299

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3 changes: 2 additions & 1 deletion bindings/dotnet/UnicornEngine/Const/X86.fs
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Original file line number Diff line number Diff line change
Expand Up @@ -290,7 +290,8 @@ module X86 =
let UC_X86_REG_FDP = 256
let UC_X86_REG_FDS = 257
let UC_X86_REG_FOP = 258
let UC_X86_REG_ENDING = 259
let UC_X86_REG_XCR0 = 259
let UC_X86_REG_ENDING = 260

// X86 instructions

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3 changes: 2 additions & 1 deletion bindings/go/unicorn/x86_const.go
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Expand Up @@ -285,7 +285,8 @@ const (
X86_REG_FDP = 256
X86_REG_FDS = 257
X86_REG_FOP = 258
X86_REG_ENDING = 259
X86_REG_XCR0 = 259
X86_REG_ENDING = 260

// X86 instructions

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3 changes: 2 additions & 1 deletion bindings/java/src/main/java/unicorn/X86Const.java
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Expand Up @@ -287,7 +287,8 @@ public interface X86Const {
public static final int UC_X86_REG_FDP = 256;
public static final int UC_X86_REG_FDS = 257;
public static final int UC_X86_REG_FOP = 258;
public static final int UC_X86_REG_ENDING = 259;
public static final int UC_X86_REG_XCR0 = 259;
public static final int UC_X86_REG_ENDING = 260;

// X86 instructions

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3 changes: 2 additions & 1 deletion bindings/pascal/unicorn/X86Const.pas
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Expand Up @@ -288,7 +288,8 @@ interface
UC_X86_REG_FDP = 256;
UC_X86_REG_FDS = 257;
UC_X86_REG_FOP = 258;
UC_X86_REG_ENDING = 259;
UC_X86_REG_XCR0 = 259;
UC_X86_REG_ENDING = 260;

// X86 instructions

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3 changes: 2 additions & 1 deletion bindings/python/unicorn/x86_const.py
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Expand Up @@ -283,7 +283,8 @@
UC_X86_REG_FDP = 256
UC_X86_REG_FDS = 257
UC_X86_REG_FOP = 258
UC_X86_REG_ENDING = 259
UC_X86_REG_XCR0 = 259
UC_X86_REG_ENDING = 260

# X86 instructions

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3 changes: 2 additions & 1 deletion bindings/ruby/unicorn_gem/lib/unicorn_engine/x86_const.rb
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Expand Up @@ -285,7 +285,8 @@ module UnicornEngine
UC_X86_REG_FDP = 256
UC_X86_REG_FDS = 257
UC_X86_REG_FOP = 258
UC_X86_REG_ENDING = 259
UC_X86_REG_XCR0 = 259
UC_X86_REG_ENDING = 260

# X86 instructions

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3 changes: 2 additions & 1 deletion bindings/zig/unicorn/x86_const.zig
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Expand Up @@ -285,7 +285,8 @@ pub const x86Const = enum(c_int) {
X86_REG_FDP = 256,
X86_REG_FDS = 257,
X86_REG_FOP = 258,
X86_REG_ENDING = 259,
X86_REG_XCR0 = 259,
X86_REG_ENDING = 260,

// X86 instructions

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1 change: 1 addition & 0 deletions include/unicorn/x86.h
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Expand Up @@ -326,6 +326,7 @@ typedef enum uc_x86_reg {
UC_X86_REG_FDP,
UC_X86_REG_FDS,
UC_X86_REG_FOP,
UC_X86_REG_XCR0,
UC_X86_REG_ENDING // <-- mark the end of the list of registers
} uc_x86_reg;

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18 changes: 18 additions & 0 deletions qemu/target/i386/unicorn.c
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Expand Up @@ -595,6 +595,10 @@ uc_err reg_read(void *_env, int mode, unsigned int regid, void *value,
CHECK_REG_TYPE(uint32_t);
*(uint32_t *)value = (uint32_t)env->segs[R_FS].base;
break;
case UC_X86_REG_XCR0:
CHECK_REG_TYPE(uint64_t);
*(uint64_t *)value = env->xcr0;
break;
}
break;

Expand Down Expand Up @@ -1092,6 +1096,10 @@ uc_err reg_read(void *_env, int mode, unsigned int regid, void *value,
CHECK_REG_TYPE(uint64_t);
*(uint64_t *)value = (uint64_t)env->segs[R_GS].base;
break;
case UC_X86_REG_XCR0:
CHECK_REG_TYPE(uint64_t);
*(uint64_t *)value = env->xcr0;
break;
}
break;
#endif
Expand Down Expand Up @@ -1482,6 +1490,11 @@ uc_err reg_write(void *_env, int mode, unsigned int regid, const void *value,
env->segs[R_GS].base = *(uint32_t *)value;
continue;
*/
case UC_X86_REG_XCR0:
CHECK_REG_TYPE(uint64_t);
env->xcr0 = *(uint64_t *)value;
cpu_sync_bndcs_hflags(env);
break;
}
break;

Expand Down Expand Up @@ -2002,6 +2015,11 @@ uc_err reg_write(void *_env, int mode, unsigned int regid, const void *value,
CHECK_REG_TYPE(uint64_t);
env->segs[R_GS].base = *(uint64_t *)value;
return 0;
case UC_X86_REG_XCR0:
CHECK_REG_TYPE(uint64_t);
env->xcr0 = *(uint64_t *)value;
cpu_sync_bndcs_hflags(env);
break;
}
break;
#endif
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