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examples: add SERV RISC-V soft CPU on Shrike-lite (SLG47910)#51

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devtyagi3909:examples/serv-riscv-shrike-lite
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examples: add SERV RISC-V soft CPU on Shrike-lite (SLG47910)#51
devtyagi3909 wants to merge 3 commits intovicharak-in:mainfrom
devtyagi3909:examples/serv-riscv-shrike-lite

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@devtyagi3909 devtyagi3909 commented Apr 12, 2026 •
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World's first documented port of a RISC-V soft CPU (SERV, ISC licence) to the Renesas SLG47910 ForgeFPGA.

Implemented on Vicharak's shrike-Lite board

terminal

Three novel toolchain findings documented in docs/toolchain_failures.md:

  1. BRAM init crash: $readmemh -> RAMSRL overflow -> compiler abort.
    Fixed: case()-based Nuclear ROM (pure LUT combinational logic).

  2. Silent PNR lobotomy: $mem register file -> RAMSRL -> Forge PNR silently fails to route -> CPU frozen at PC=0x00, no error. Fixed: (* ram_style = 'registers' *) -> standard DFF array.

  3. IO Planner conflict: manually assigning GPIO17/18 breaks auto- routing. FPGA GPIO17/18 are the only pins hardwired to RP2040 GPIO14/15 via PCB 0-ohm resistors. Leave result signals unassigned in IO Planner -- Yosys routes them automatically.

Verified on hardware:
RP2040 GPIO14 = 3.3V, GPIO15 = 3.3V -> result = 0b11 = 3
Thonny: 'SERV RISC-V computed: 1 + 2 = 3'

Resource utilisation: 516/1120 LUTs (46%), 230/1120 FFs (21%)

Board: Shrike-lite (SLG47910 + RP2040)
Tools: Go Configure Software Hub + Thonny MicroPython

What does this PR do?

Type of change

  • New example
  • Bug fix
  • Documentation update
  • Firmware improvement
  • Tooling / CI
  • Other

Board(s) tested on

  • Shrike-Lite (RP2040)
  • Shrike (RP2350)
  • Shrike-fi (ESP32-S3)
  • Not hardware-dependent

Checklist

For all PRs:

  • I have tested my changes
  • My code follows the project's style guidelines
  • I have updated relevant documentation (if applicable)

For new examples:

  • Follows the standard folder structure (ffpga/, firmware/, bitstream/, README.md)
  • Includes pre-built bitstream in bitstream/
  • Includes README with difficulty level, compatibility table, and expected output
  • Firmware is platform-agnostic (#ifdef / sys.platform) — see guide
  • Tested with ShrikeFlash

For firmware changes:

  • Works on RP2040
  • Works on ESP32-S3 (or marked as untested in README)
  • No hardcoded pin numbers (uses platform config block)

Related issue

Screenshots / serial output

@devtyagi3909
examples: add SERV RISC-V soft CPU on Shrike-lite (SLG47910)
d0f8541 
World's first documented port of a RISC-V soft CPU (SERV, ISC licence)
to the Renesas SLG47910 ForgeFPGA.

Three novel toolchain findings documented in docs/toolchain_failures.md:

  1. BRAM init crash: $readmemh -> RAMSRL overflow -> compiler abort.
     Fixed: case()-based Nuclear ROM (pure LUT combinational logic).

  2. Silent PNR lobotomy: $mem register file -> RAMSRL -> Forge PNR
     silently fails to route -> CPU frozen at PC=0x00, no error.
     Fixed: (* ram_style = 'registers' *) -> standard DFF array.

  3. IO Planner conflict: manually assigning GPIO17/18 breaks auto-
     routing. FPGA GPIO17/18 are the only pins hardwired to RP2040
     GPIO14/15 via PCB 0-ohm resistors. Leave result signals unassigned
     in IO Planner -- Yosys routes them automatically.

Verified on hardware:
  RP2040 GPIO14 = 3.3V, GPIO15 = 3.3V -> result = 0b11 = 3
  Thonny: 'SERV RISC-V computed: 1 + 2 = 3'

Resource utilisation: 516/1120 LUTs (46%), 230/1120 FFs (21%)

Board: Shrike-lite (SLG47910 + RP2040)
Tools: Go Configure Software Hub + Thonny MicroPython
@dpks2003 dpks2003 self-requested a review April 12, 2026 17:28
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dpks2003 commented Apr 12, 2026 •
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Hey @devtyagi3909 Thank you for the contribution
Getting the serv working on the Shrike is a great thing

We will be doing the board testing before merging it
However there are a few thing that you need to change in the PR

  1. First and most import the main <project_name>.ffpga file is missing from the PR that is the main project file please add that.
  2. Please change the project name to shrike_serv as adding the shirke-Lite has no meaning as it can be ported to other version as well.
  3. please add the micropyhton firmware in the micropython sun directory something like firmware/micropython and keep the file name same as project name.
  4. Change the bitstream name same as <project_name>.bin and please remove the docs folder add it to the README.md itself.
  5. Please remove the unnecessary .git ignore file from the PR.

Regards
Deepak

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dpks2003 commented Apr 12, 2026

@UpendraReddi @pallaviphunde2003 please test this example on board onces the requested changes are done.

dpks2003
dpks2003 requested changes Apr 12, 2026
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read above mentioned comments

@devtyagi3909
examples/shrike_serv: address reviewer feedback
c3cb73f 
- Rename project to shrike_serv (board-agnostic)
- Add shrike_serv.ffpga (Go Configure project file)
- Move firmware to firmware/micropython/shrike_serv.py
- Rename bitstream to shrike_serv.bin
- Remove docs/ folder, merge toolchain notes into README.md
- Remove .gitignore
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devtyagi3909 commented Apr 13, 2026

Hi @dpks2003, all 5 changes have been addressed:

Added shrike_serv.ffpga (Go Configure project file)
Renamed project folder to shrike_serv (board-agnostic)
Firmware moved to firmware/micropython/shrike_serv.py
Bitstream renamed to shrike_serv.bin
docs/ removed, toolchain analysis merged into README.md
.gitignore removed

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UpendraReddi commented Apr 13, 2026 •
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@devtyagi3909 Please place the .v files in the src folder in the ffpga folder and move the shrike_serv.ffpga file to the shrike_serv folder from the ffpga folder.

Please follow this standard. https://github.com/vicharak-in/shrike?tab=contributing-ov-file#submitting-an-example

@dpks2003 dpks2003 linked an issue Apr 13, 2026 that may be closed by this pull request
SERV - serial RISCV Core is not compiling using renesas ForgeFPGA toolchain #13
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@devtyagi3909
examples/shrike_serv: fix structure per contributing guide + add comp…
c800254 
…utation docs

- Move .v files to ffpga/src/ per standard folder structure

- Move shrike_serv.ffpga to example root

- Add images/output.JPG (verified serial output)

- Update README: add custom computation guide + instruction encoding table
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devtyagi3909 commented Apr 13, 2026

Hi @UpendraReddi, all changes done:

.v files moved to ffpga/src/
shrike_serv.ffpga moved to example root
images/output.JPG added (result.png)
README updated with custom computation guide and instruction encoding table

UpendraReddi
UpendraReddi suggested changes Apr 17, 2026
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Please do these requested changes.

Please ignore this

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SERV - serial RISCV Core is not compiling using renesas ForgeFPGA toolchain

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