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Pin AM62L LPDDR4 repro and allow 8-layer Pipeline 10 inputs - #2143

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ShiboSoftwareDev merged 2 commits into
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agent/pin-srj29-sample021-retry
Aug 18, 2026
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Pin AM62L LPDDR4 repro and allow 8-layer Pipeline 10 inputs#2143
ShiboSoftwareDev merged 2 commits into
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agent/pin-srj29-sample021-retry

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@ShiboSoftwareDev

@ShiboSoftwareDev ShiboSoftwareDev commented Aug 18, 2026 •
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Summary

  • pin @tscircuit/dataset-srj29-ddr3-bga-pairs to 585c3abd4c6ce4be52bbc430b1d5e6dcc9b4ea30
  • add the exact 8-layer AM62L32-to-LPDDR4 sample as SRJ29 sample 021
  • remove Pipeline 10's artificial 12-layer minimum so it uses the board's actual copper-layer count

Why

The 12-layer check came from the original roomy SRJ29 fixture, not from a fanout-solver or Pipeline 9 requirement. It rejected the real 8-layer reproduction before fanout began.

Validation

  • focused Pipeline 10 tests: 3 passed, including a 19 ms 8-layer initialization check
  • bun run format:check
  • bunx tsc --noEmit
  • sample 021 was not solved locally; the regression check uses a one-connection variant of the existing fast fixture

This PR supersedes #2142, whose deployment coincided with transient GitHub tarball 504 errors during dependency installation.

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vercel Bot commented Aug 18, 2026 •
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Project Deployment Actions Updated (UTC)
capacity-node-autorouter Ready Ready Preview Aug 18, 2026 4:05am

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tscircuitbot commented Aug 18, 2026

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Benchmark This PR

Run benchmarks by commenting on this PR:

/benchmark [benchmark.sh args...]
/benchmark-long [benchmark.sh args...]
/benchmark-all
/benchmark --same-machine
/benchmark-all --same-machine

Comment /benchmark to run the default dataset, or append any arguments accepted by ./benchmark.sh.
Comment /benchmark-long for an 8-vCPU run that defaults to 8 workers and has an eight-hour timeout.
Comment exactly /benchmark-all to start separate workflow runs and result comments for the default dataset plus srj18, srj19, srj20, srj21, and srj23.
Append --same-machine to /benchmark or /benchmark-all to compare current main and the PR head sequentially on the same 8-vCPU Blacksmith runner.

Everything after /benchmark or /benchmark-long is safely forwarded to ./benchmark.sh, except --profile-solvers, which enables profile comparison tables, and --same-machine, which enables the paired runner.
Examples: /benchmark --dataset 18 --sample-timeout 2000s, /benchmark --pipeline 10 --dataset 29, /benchmark --pipeline 10 --dataset 29 --sample 1, /benchmark --pipeline 7 --limit 20, /benchmark all 20 --concurrency 8, /benchmark --same-machine, /benchmark-all --same-machine, and /benchmark-long --dataset 18.

Use /update-snapshots (or /us) to run BUN_UPDATE_SNAPSHOTS=1 bun test --timeout 120_000 on the PR branch and auto-commit snapshot updates.
Use /usf to read recent failed test files, update and verify their exact CI test shards, and auto-commit only their snapshots. It uses the configured fast benchmark runner by default; use /usf --ubuntu-latest for GitHub-hosted x64 CI parity.

Any PR whose title contains [BENCHMARK TEST] will automatically run one default-dataset benchmark on PR updates; it does not post a PR result comment.

@ShiboSoftwareDev ShiboSoftwareDev changed the title Pin exact AM62L LPDDR4 SRJ29 reproduction Pin AM62L LPDDR4 repro and allow 8-layer Pipeline 10 inputs Aug 18, 2026
@ShiboSoftwareDev

ShiboSoftwareDev commented Aug 18, 2026

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/benchmark --dataset 29 --pipeline 10

@tscircuitbot

tscircuitbot commented Aug 18, 2026 •
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29 Results

Main vs PR

Dataset: srj29 · Scenarios: 21 · Effort: 1x effort

Solver Metric Main PR Change
Pipeline10 Completion n/a 14.3% (🕒52.4%) n/a
Pipeline10 Relaxed DRC pass n/a 14.3% (🕒52.4%) n/a
Pipeline10 Timeouts n/a 11 n/a
Pipeline10 P50 time n/a 360.0s n/a
Pipeline10 P60 time n/a 360.0s n/a
Pipeline10 P70 time n/a 360.0s n/a
Pipeline10 P80 time n/a 360.0s n/a
Pipeline10 P90 time n/a 360.0s n/a
Pipeline10 P95 time n/a 360.0s n/a
Pipeline10 Average vias n/a 45.00 n/a

Timing percentiles include solved and timed-out samples. Negative timing changes are faster.

PR run details
Solver Sample Status Via Time Relaxed DRC Error Delta
Pipeline10 1 Solved 50 324.3s Passed
Pipeline10 2 Timeout 360.0s Failed
AutoroutingStagePhase: autoroutingPipelineSolver
Timed out after 360.0s
Last progress: phase=autoroutingPipelineSolver, solver=AutoroutingStage, pipelineIterations=621776, phaseIterations=621696, pipelineProgress=75%, phaseProgress=0%
Pipeline10 3 Failed 176.8s Failed
AutoroutingStagePhase: autoroutingPipelineSolver
AutoroutingStage error: Error: Pipeline9 cannot exactly repair through-obstacle preloaded trace "fanout:DDR3_a2_dram_dq13:source-1"
Pipeline10 4 Failed 194.5s Failed
AutoroutingStagePhase: autoroutingPipelineSolver
AutoroutingStage error: Error: Pipeline9 expected one nearest stitched route for changed preloaded section "tscircuit_preloaded_trace:["fanout:DDR3_k1_ram_odt:source-1",1]", got 0
Pipeline10 5 Timeout 360.0s Failed
AutoroutingStagePhase: autoroutingPipelineSolver
Timed out after 360.0s
Last progress: phase=autoroutingPipelineSolver, solver=AutoroutingStage, pipelineIterations=2399185, phaseIterations=2399169, pipelineProgress=75%, phaseProgress=0%
Pipeline10 6 Failed 234.6s Failed
AutoroutingStagePhase: autoroutingPipelineSolver
AutoroutingStage error: Error: Pipeline9 cannot exactly repair through-obstacle preloaded trace "fanout:DDR3_d3_fpga_ram_udm:source-0"
Pipeline10 7 Failed 236.9s Failed
AutoroutingStagePhase: autoroutingPipelineSolver
SelectiveReripTinyHyperGraphSolverWithStableInitialAssignments ran out of iterations
Pipeline10 8 Timeout 360.0s Failed
AutoroutingStagePhase: autoroutingPipelineSolver
Timed out after 360.0s
Last progress: phase=autoroutingPipelineSolver, solver=AutoroutingStage, pipelineIterations=58842, phaseIterations=58810, pipelineProgress=75%, phaseProgress=0%
Pipeline10 9 Timeout 360.0s Failed
AutoroutingStagePhase: autoroutingPipelineSolver
Timed out after 360.0s
Last progress: phase=autoroutingPipelineSolver, solver=AutoroutingStage, pipelineIterations=722264, phaseIterations=722248, pipelineProgress=75%, phaseProgress=0%
Pipeline10 10 Timeout 360.0s Failed
AutoroutingStagePhase: autoroutingPipelineSolver
Timed out after 360.0s
Last progress: phase=autoroutingPipelineSolver, solver=AutoroutingStage, pipelineIterations=1105884, phaseIterations=1105866, pipelineProgress=75%, phaseProgress=0%
Pipeline10 11 Failed 138.7s Failed
AutoroutingStagePhase: autoroutingPipelineSolver
AutoroutingStage error: Error: Pipeline9 could not reconnect mutated preloaded segment "DDR3_a3_i_mx6ull_main_ram_ddr3_dram_data15_fixed_27_1"
Pipeline10 12 Timeout 360.0s Failed
AutoroutingStagePhase: autoroutingPipelineSolver
Timed out after 360.0s
Last progress: phase=autoroutingPipelineSolver, solver=AutoroutingStage, pipelineIterations=54538, phaseIterations=54505, pipelineProgress=75%, phaseProgress=0%
Pipeline10 13 Timeout 360.0s Failed
AutoroutingStagePhase: autoroutingPipelineSolver
Timed out after 360.0s
Last progress: phase=autoroutingPipelineSolver, solver=AutoroutingStage, pipelineIterations=71667, phaseIterations=71651, pipelineProgress=75%, phaseProgress=0%
Pipeline10 14 Failed 317.6s Failed
AutoroutingStagePhase: autoroutingPipelineSolver
SelectiveReripTinyHyperGraphSolverWithStableInitialAssignments ran out of iterations
Pipeline10 15 Solved 46 324.1s Passed
Pipeline10 16 Timeout 360.0s Failed
AutoroutingStagePhase: autoroutingPipelineSolver
Timed out after 360.0s
Last progress: phase=autoroutingPipelineSolver, solver=AutoroutingStage, pipelineIterations=2125719, phaseIterations=2125691, pipelineProgress=75%, phaseProgress=0%
Pipeline10 17 Timeout 360.0s Failed
AutoroutingStagePhase: autoroutingPipelineSolver
Timed out after 360.0s
Last progress: phase=autoroutingPipelineSolver, solver=AutoroutingStage, pipelineIterations=2230302, phaseIterations=2230270, pipelineProgress=75%, phaseProgress=0%
Pipeline10 18 Solved 39 345.5s Passed
Pipeline10 19 Timeout 360.0s Failed
AutoroutingStagePhase: autoroutingPipelineSolver
Timed out after 360.0s
Last progress: phase=autoroutingPipelineSolver, solver=AutoroutingStage, pipelineIterations=566798, phaseIterations=566780, pipelineProgress=75%, phaseProgress=0%
Pipeline10 20 Timeout 360.0s Failed
AutoroutingStagePhase: autoroutingPipelineSolver
Timed out after 360.0s
Last progress: phase=autoroutingPipelineSolver, solver=AutoroutingStage, pipelineIterations=328755, phaseIterations=328739, pipelineProgress=75%, phaseProgress=0%
Pipeline10 21 Failed 20.7s Failed
FanoutStagePhase: firstBgaFanoutSolver
FanoutSolver: best layer assignment routed 9/33 connections

Workflow: View run
Artifact: https://github.com/tscircuit/tscircuit-autorouter/actions/runs/32102741788

@ShiboSoftwareDev
ShiboSoftwareDev marked this pull request as ready for review August 18, 2026 05:27
@ShiboSoftwareDev
ShiboSoftwareDev requested a review from 0hmX August 18, 2026 05:34
@ShiboSoftwareDev

ShiboSoftwareDev commented Aug 18, 2026

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/benchmark --dataset 29 --pipeline 10 --sample-timeout 900s

@tscircuitbot

tscircuitbot commented Aug 18, 2026 •
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29 Results

Main vs PR

Dataset: srj29 · Scenarios: 21 · Effort: 1x effort

Solver Metric Main PR Change
Pipeline10 Completion n/a 47.6% (🕒14.3%) n/a
Pipeline10 Relaxed DRC pass n/a 33.3% (🕒14.3%) n/a
Pipeline10 Timeouts n/a 3 n/a
Pipeline10 P50 time n/a 598.8s n/a
Pipeline10 P60 time n/a 694.0s n/a
Pipeline10 P70 time n/a 747.3s n/a
Pipeline10 P80 time n/a 843.4s n/a
Pipeline10 P90 time n/a 900.0s n/a
Pipeline10 P95 time n/a 900.0s n/a
Pipeline10 Average vias n/a 49.20 n/a

Timing percentiles include solved and timed-out samples. Negative timing changes are faster.

PR run details
Solver Sample Status Via Time Relaxed DRC Error Delta
Pipeline10 1 Solved 50 329.7s Passed
Pipeline10 2 Solved 51 516.4s Passed
Pipeline10 3 Failed 211.9s Failed
AutoroutingStagePhase: autoroutingPipelineSolver
AutoroutingStage error: Error: Pipeline9 cannot exactly repair through-obstacle preloaded trace "fanout:DDR3_a2_dram_dq13:source-1"
Pipeline10 4 Failed 194.2s Failed
AutoroutingStagePhase: autoroutingPipelineSolver
AutoroutingStage error: Error: Pipeline9 expected one nearest stitched route for changed preloaded section "tscircuit_preloaded_trace:["fanout:DDR3_k1_ram_odt:source-1",1]", got 0
Pipeline10 5 Solved 53 598.8s Failed
Pipeline10 6 Failed 235.3s Failed
AutoroutingStagePhase: autoroutingPipelineSolver
AutoroutingStage error: Error: Pipeline9 cannot exactly repair through-obstacle preloaded trace "fanout:DDR3_d3_fpga_ram_udm:source-0"
Pipeline10 7 Failed 206.4s Failed
AutoroutingStagePhase: autoroutingPipelineSolver
SelectiveReripTinyHyperGraphSolverWithStableInitialAssignments ran out of iterations
Pipeline10 8 Timeout 900.0s Failed
AutoroutingStagePhase: autoroutingPipelineSolver
Timed out after 900.0s
Last progress: phase=autoroutingPipelineSolver, solver=AutoroutingStage, pipelineIterations=1785408, phaseIterations=1785376, pipelineProgress=75%, phaseProgress=0%
Pipeline10 9 Timeout 900.0s Failed
AutoroutingStagePhase: autoroutingPipelineSolver
Timed out after 900.0s
Last progress: phase=autoroutingPipelineSolver, solver=AutoroutingStage, pipelineIterations=722263, phaseIterations=722247, pipelineProgress=75%, phaseProgress=0%
Pipeline10 10 Solved 55 758.4s Failed
Pipeline10 11 Failed 151.5s Failed
AutoroutingStagePhase: autoroutingPipelineSolver
AutoroutingStage error: Error: Pipeline9 could not reconnect mutated preloaded segment "DDR3_a3_i_mx6ull_main_ram_ddr3_dram_data15_fixed_27_1"
Pipeline10 12 Solved 53 418.6s Passed
Pipeline10 13 Timeout 900.0s Failed
AutoroutingStagePhase: autoroutingPipelineSolver
Timed out after 900.0s
Last progress: phase=autoroutingPipelineSolver, solver=AutoroutingStage, pipelineIterations=867173, phaseIterations=867157, pipelineProgress=75%, phaseProgress=0%
Pipeline10 14 Failed 299.6s Failed
AutoroutingStagePhase: autoroutingPipelineSolver
SelectiveReripTinyHyperGraphSolverWithStableInitialAssignments ran out of iterations
Pipeline10 15 Solved 46 324.7s Passed
Pipeline10 16 Solved 47 739.9s Passed
Pipeline10 17 Solved 53 682.6s Failed
Pipeline10 18 Solved 39 331.4s Passed
Pipeline10 19 Failed 781.9s Failed
AutoroutingStagePhase: autoroutingPipelineSolver
AutoroutingStage error: Error: Pipeline9 could not reconnect mutated preloaded segment "DDR3_c3_ddr3_dq9_fixed_29_1"
Pipeline10 20 Solved 45 378.9s Passed
Pipeline10 21 Failed 20.8s Failed
FanoutStagePhase: firstBgaFanoutSolver
FanoutSolver: best layer assignment routed 9/33 connections

Workflow: View run
Artifact: https://github.com/tscircuit/tscircuit-autorouter/actions/runs/32112590206

@0hmX

0hmX commented Aug 18, 2026

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lgtm but will need review for @seveibar not sure why that limit was even present

@ShiboSoftwareDev

ShiboSoftwareDev commented Aug 18, 2026

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lgtm but will need review for @seveibar not sure why that limit was even present

Wasn't needed, just AI slop

@ShiboSoftwareDev
ShiboSoftwareDev merged commit c7ec314 into main Aug 18, 2026
28 of 29 checks passed
@tscircuitbot

tscircuitbot commented Aug 18, 2026

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Thank you for your contribution! 🎉

PR Rating: ⭐⭐⭐
Impact: Major

Track your contributions and see the leaderboard at: tscircuit Contribution Tracker

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