⎔ Using the program ModelSim-Altera, to execute a Synchronous Counter with Asynchronous and Synchronous Reset project by implementing a 2 Bit, 4 Bit, 6 Bit, and 11 Bit for counters by using VHDL code.
-
Updated
Feb 24, 2025
#
synchronous-counter
Here are 6 public repositories matching this topic...
basic implementation of logic structures using verilog (revising github)
registers pipo d-flipflop full-adder sipo sequence-detector siso piso verilog-testbenches synchronous-counter priority-encoder jk-flipflop t-flipflop sr-flip-flop full-subtractor half-subtractor
-
Updated
Feb 29, 2024 - Verilog
circuits of sequential elements
-
Updated
Nov 7, 2025
Verilog code for combinational and sequential circuits
verilog bcd mux hdl multiplexer verilog-hdl moore-machine adders mealy-machine-code flipflop latches synchronous-counter sequentialcircuits shift-registers 7segmentdisplay digitalcircuits flipflop-codes subtractors
-
Updated
Dec 2, 2025 - Verilog
Assignment 6, Digital Logic Design Lab, Spring 2021, IIT Bombay
-
Updated
Mar 21, 2021 - VHDL
This repository contains a collection of Digital Logic Design counters designed and simulated using NI Multisim.
digital-clock dld digital-logic-simulator synchronous-counter digital-logic-design-lab digital-logic-circuits asynchronous-counter
-
Updated
Jan 8, 2026
Improve this page
Add a description, image, and links to the synchronous-counter topic page so that developers can more easily learn about it.
Add this topic to your repo
To associate your repository with the synchronous-counter topic, visit your repo's landing page and select "manage topics."