AMD SOF stack fixes and improvements related to IPC flags #5642
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Firmware will set dsp_ack to 1 when firmware sends response for the IPC command issued by host. Similarly dsp_msg flag will be updated to 1. During ACP D0 entry sequence, during firmware run sequence, Once the firmware sends the FW_READY message in the acp irq thread, dsp_ack_write register relative offset read from scratch memory points to garbage value. In this case, fw_state is SOF_FW_BOOT_READY_OK results in else condition execution printing below dmesg log. "IPC reply before FW_BOOT_COMPLETE". This is not an expected sequence. Fix the condition checks for ipc flags. Fixes: 738a2b5 ("ASoC: SOF: amd: Add IPC support for ACP IP block") Signed-off-by: Vijendar Mukunda <[email protected]> Tested-by: Umang Jain <[email protected]>
As per design, set IPC conf structure flags to zero during acp init sequence. Signed-off-by: Vijendar Mukunda <[email protected]> Tested-by: Umang Jain <[email protected]>
Author
ranj063
approved these changes
Jan 10, 2026
bardliao
reviewed
Jan 12, 2026
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| dsp_msg = snd_sof_dsp_read(sdev, ACP_DSP_BAR, ACP_SCRATCH_REG_0 + dsp_msg_write); | ||
| if (dsp_msg) { | ||
| if (dsp_msg == 1) { |
Collaborator
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What does 1 mean? Can we use a #define or add some comment here and line 191?
Author
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dsp_msg flag is set to 1 by Firmware when sends an IPC. Similarly dsp_ack will be set to 1 by firmware when it responds to host IPC message. Will use macros for the same
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This patch series consists of fixes and improvement related to IPC flags handling.