v0.8.2

• Instantiate RO bit field module for reserved bit field to fix #134

v0.8.1

• fix issue #132

v0.8.0

• Implemented new configuration parameters
  • array_port_format: Specify format of array ports (#125)
    • unpacked: Use unpacked array
    • vectored: Use one-dimensional vector
  • unfold_sv_interface_port: If set true, SV interface ports are unfolded to each signal ports (#124)
• Removed IRQ feature (#128)
• Specify data type of in/out ports of generated RTL (#126)

v0.7.2

• Implemented the internal bus bridge module for AXI4 Lite (#41, #117, #121)
  • Special thanks to Adrian Fiergolski (@adrianf0) !

v0.7.1

• fixed CI error with Ruby 2.3.2 and 2.3.3 (#115)

v0.7.0

• Removed Ruby 2.2 support (#112)
• Replaced ERB engine from BabyErubis to Erubi (#60)

v0.6.4

Changes

• Update copyright year
• Remove Ruby 2.0 and 2.1 support (#59)

v0.6.2

Fixed Issues

• Lint Error of rggen_bus_splitter module
  • refer to taichi-ishitani/rggen-building-block-rtl#5

Changes

• Abort and display error message when RgGen::RuntimeError or OptParse::ParseError are raised (#43, #58)

v0.6.1

Fixed Issues

• Instance names of a register module and a bit field module may be overlapped (#56)