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This adds support for building fpganes for Nexys4 with FuseSoC. How to use: #install fusesoc pip install fuseseoc #Create and enter a new workspace mkdir workspace && cd workspace #Add fpganes as a library to the workspace fusesoc library add fpganes /path/to/fpganes #...if repo is available locally or... fusesoc library add fpganes https://github.com/strigeus/fpganes #...to get the upstream repo #To build, run fusesoc run --target=nexys4 fpganes
This adds an additional FuseSoC target that creates a hardened macro GDSII file of the APU using OpenLane. It also adds a github action to automatically run this on every push to the repo
This adds an additional FuseSoC target that creates a hardened macro GDSII file of the PPU using OpenLane. It also adds a github action to automatically run this on every push to the repo
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Adding FuseSoC support for building an FPGA bitstream for Nexys4 and producing a GDSII file of the APU module.
The latter might need some explanation. I noticed it has been used as an example in the openlane repo and with the work I'm doing with adding FuseSoC support to Openlane we thought it would be nice to upstream asicification of all the example designs to their proper places