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You must be logged in to vote 💡 [RFC] FAST_MUL_REG: technology-agnostic pipelined fast multiplier (working implementation, feedback wanted)
optimizationMake things faster, smaller and more efficient customizationTailoring the core to your needs -
You must be logged in to vote 💬 XBUS Timeout
enhancementNew feature or request HWHardware-related customizationTailoring the core to your needs -
You must be logged in to vote 💡 ADD XIP MODULE
enhancementNew feature or request customizationTailoring the core to your needs -
You must be logged in to vote 💬 Certus-NX port
troubleshootingSomething is not working as expected customizationTailoring the core to your needs -
You must be logged in to vote 🙏 Trouble Connecting NEORV32 on PolarFire FPGA via JTAG (OpenOCD)
customizationTailoring the core to your needs -
You must be logged in to vote 🙏 Using onboard RAM instead of IMEM for the bootloading
customizationTailoring the core to your needs -
You must be logged in to vote 🙏 CFU minimum clock cycles
HWHardware-related optimizationMake things faster, smaller and more efficient customizationTailoring the core to your needs -
You must be logged in to vote 🙏 Problems with missing custom files used for CFS in Vivado IP block
customizationTailoring the core to your needs -
You must be logged in to vote 🙏 Replicating existing modules - further extend UART ports
HWHardware-related SWSoftware-related howtoHands-on expertise / tutorial / user guide customizationTailoring the core to your needs