Add Zvbc32e and Zvkgs specifications (into vector crypto chapter)

[nibrunieAtSi5]

Following the ARC review on #1306, I am opening this pull-request to integrate the specifications following the ARC recommendations.

Eventually this PR will represent the frozen specifications for both Zvbc32e and Zvkgs.

RVIA tracking

This pull requests draft the changes associated with two fast track extensions for vector crypto.

Fast track is tracked in https://riscv.atlassian.net/browse/RVS-1915

New features:

• Zvbc32e: Extending vclmul[h].v[vh] instruction to support SEW=32-bit, 16-bit and 8-bit values. Zvbc32e is available standalone (ELEN >= 32) or in addition to Zvbc (ELEN >= 64). no new encoding
• Zvkgs: Adding .vs variants to vghsh and vgmul; should depend on Zvkg; new encodings

Related changes:

• spike-isa-sim modifications
  • add support for Zvbc32e and Zvkgs: Vector crypto additional riscv-software-src/riscv-isa-sim#1748
• encoding proposal in riscv-opcodes repo: Vector crypto additional extensions: Zvbc32e and Zvkgs riscv-opcodes#270
• adapt vector crypto code samples for Zvbce32 https://github.com/riscv/riscv-crypto/blob/main/doc/vector/code-samples/zvbc-test.c
• adapt vector crypto code samples for Zvkgs https://github.com/riscv/riscv-crypto/blob/main/doc/vector/code-samples/zvkg-test.c
• Sail models
  • Zvkgs: Adding support for (project) fast track extension Zvkgs sail-riscv#1017
  • Zvbc32e: Adding support for Zvbc32e sail-riscv#931
• Compiler support
  • LLVM: [WIP][RISC-V] prototyping intrinsic support for Zvbc32e and Zvkgs llvm/llvm-project#128243
  • GCC: TBD
• rvv-intrinsics support: Adding intrinsics generation support for extension Zvbc32e and Zvkgs riscv-non-isa/rvv-intrinsic-doc#420

History

During the specification process for vector crypto 1.0.0 a few items had to be discarded because they appeared too late in the process. This fast track extension tries to address some of them.

The official demand that will be discussed in the Task Group and submitted to the Unpriv Committee is being drafter here: https://docs.google.com/document/d/1zpYhnZi2NxhjfcBGvPOy0oDhx6lTXchscG17Qcl6wv8/edit?usp=sharing

This pull request follows a previous PR against riscv-isa-manual, #1306, which itself was the follow-up to a pull request started on the riscv-crypto repo: riscv/riscv-crypto#362.

[aswaterman]

Please replace all of the <= with {le} and >= with {ge}.

[nibrunieAtSi5]

done in 7cb19f0

[nibrunieAtSi5]

Suggested change

	It is not suitable for implementations with small `ELEN` (32) and incurs some inefficiencies for algorithms where at least one of the multiplication operands is limited to 32 bits (or less).
	It is not suitable for implementations with small `ELEN` (32) and incurs some inefficiencies for algorithms where at least one of the multiplication operands is limited to 32-bit (or narrower).