Configurable delay of chip-select to clock-start#29
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Prevents performance degradations (FIFO bubbles) in situation where the system and PHY are running on the same clock.
Prevents performance degradations (FIFO bubbles) in situation where the system and PHY are running on the same clock.
Acording to spec: t_DSV (data strobe valid) which is the time from CS# going low to the first hyperbus clock can be at most 2 clock periods long (12ns@166MHz). This shrinks the RWDS valid window down to one period centered on CA4 (5th data transaction). Meaning it is valid around the 3rd rising edge of CK. Problem: With additional routing delay this may cause the RWDS sample register (clocked by clk_i) to miss the stable period of RWDS. Solution: Delaying the clock is allowed and gives RWDS more time to arrive and creates a larger stable window. It is possible to set this to zero to increase throughput.
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Requires #28
Adds a config option to configure the number of cycles the clock-start is delayed after the chip-select is asserted.
This can make the implementation more robust against potential timing problems.
The cost is a few GE and it is possible to perfectly recreate the previous timings.