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Add cockpitrc and default croc.flist Full Flow #15: Pull request #35 synchronize by phsauter
4m 12s phsauter/cockpitrc
phsauter/cockpitrc
4m 12s
yosys: add a default croc.flist Short Flow #61: Commit 684e4cf pushed by phsauter
6m 46s phsauter/cockpitrc
phsauter/cockpitrc
6m 46s
Add cockpitrc and default croc.flist Full Flow #14: Pull request #35 opened by phsauter
4m 5s phsauter/cockpitrc
phsauter/cockpitrc
4m 5s
yosys: add a default croc.flist Short Flow #60: Commit 09dd50e pushed by phsauter
6m 28s phsauter/cockpitrc
phsauter/cockpitrc
6m 28s
hw: fix signal forced to inout warning Short Flow #59: Commit 3ce7cb1 pushed by phsauter
7m 2s phsauter/cockpitrc
phsauter/cockpitrc
7m 2s
sw: small error correction in the print library Short Flow #58: Commit 4f72eb1 pushed by thommythomaso
6m 43s main
main
6m 43s
sw: small error correction in the print library Full Flow #13: Pull request #34 opened by piussieber
1h 15m 44s main
main
1h 15m 44s
CI: add ArtistIC to the full-flow CI Short Flow #57: Commit eddba42 pushed by phsauter
6m 29s main
main
6m 29s
CI: add ArtistIC to the full-flow CI Full Flow #12: Pull request #32 synchronize by thommythomaso
57m 16s tbenz/artistic
tbenz/artistic
57m 16s
CI: add ArtistIC to the full-flow CI Short Flow #56: Commit 9d7ab9a pushed by thommythomaso
6m 30s tbenz/artistic
tbenz/artistic
6m 30s
test: add loopback test Short Flow #55: Commit 628123f pushed by phsauter
6m 18s phsauter/uart
phsauter/uart
6m 18s
CI: add ArtistIC to the full-flow CI Full Flow #11: Pull request #32 synchronize by thommythomaso
59m 33s tbenz/artistic
tbenz/artistic
59m 33s
CI: add ArtistIC to the full-flow CI Short Flow #54: Commit 840242c pushed by thommythomaso
6m 41s tbenz/artistic
tbenz/artistic
6m 41s
CI: add ArtistIC to the full-flow CI Full Flow #10: Pull request #32 synchronize by thommythomaso
1h 1m 36s tbenz/artistic
tbenz/artistic
1h 1m 36s
CI: add ArtistIC to the full-flow CI Short Flow #53: Commit c5808e8 pushed by thommythomaso
10m 18s tbenz/artistic
tbenz/artistic
10m 18s
WIP: add new SystemVerilog UART Short Flow #52: Commit bbd563f pushed by phsauter
14m 48s phsauter/uart
phsauter/uart
14m 48s
ci: fix full-flow artifacts Short Flow #50: Commit a8223f5 pushed by phsauter
17m 33s phsauter/ci-fix
phsauter/ci-fix
17m 33s
WIP: add new SystemVerilog UART Short Flow #49: Commit eccb118 pushed by phsauter
37m 57s phsauter/uart
phsauter/uart
37m 57s
Add ex02 files Short Flow #8: Commit b3a944e pushed by ezelioli
6m 39s ex02
ex02
6m 39s
sw/link.ld: adjust memory map to 4k of SRAM Short Flow #7: Commit fb59f5b pushed by phsauter
6m 36s main
main
6m 36s
openroad: report final metrics Short Flow #6: Commit 021fae7 pushed by phsauter
6m 59s main
main
6m 59s
[Openroad] Remove filler cells when writing lvs netlist Short Flow #5: Commit e925413 pushed by hopang-0221
7m 32s hp/lvs
hp/lvs
7m 32s
Openroad: Report final metrics Full Flow #4: Pull request #31 opened by TheMightyDuckOfDoom
56m 58s TheMightyDuckOfDoom:openroad-final-metrics
TheMightyDuckOfDoom:openroad-final-metrics
56m 58s
Adjust memory map in sw/link.ld to 4k of SRAM for default config with 2 banks Full Flow #3: Pull request #30 opened by TheMightyDuckOfDoom
1h 5m 13s TheMightyDuckOfDoom:default-link-fix
TheMightyDuckOfDoom:default-link-fix
1h 5m 13s
ci: add initial short and full flows Short Flow #4: Commit 17495a6 pushed by phsauter
7m 12s main
main
7m 12s
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