Add ex02 files

Author: ezelioli

ex02/ex_BD_basic_principles.odp

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+// Copyright 2024 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+
+module cdc_2phase (
+  input  logic scr_clk_i,
+  input  logic scr_valid_i,
+  output logic scr_ready_o,
+
+  input  logic dst_clk_i,
+  output logic dst_valid_o,
+  input  logic dst_ready_i
+);
+
+  logic async_req;
+  logic async_ack;
+
+  logic src_req_q, src_ack_q;
+  logic dst_req_q, dst_ack_q;
+
+  always_ff @(posedge scr_clk_i) begin
+    src_ack_q <= async_ack;
+  end
+
+  always_ff @(posedge dst_clk_i) begin
+    dst_req_q <= async_req;
+  end
+
+  always_ff @(posedge scr_clk_i) begin
+    if (scr_valid_i && scr_ready_o) begin
+      src_req_q  <= ~src_req_q;
+    end
+  end
+
+  always_ff @(posedge dst_clk_i) begin
+    if (dst_valid_o && dst_ready_i) begin
+      dst_ack_q  <= ~dst_ack_q;
+    end
+  end
+
+  assign scr_ready_o = (src_req_q == src_ack_q);
+  assign dst_valid_o = (dst_ack_q != dst_req_q);
+  assign async_req = src_req_q;
+  assign async_ack = dst_ack_q;
+
+endmodule

ex02/ex_BD_symbol_library.xml

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+// Copyright 2024 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+
+module crc_hasher (
+  input        clk_i,
+  input        rst_ni,
+  input  [7:0] data_i,
+  input        valid_i,
+  output       ready_o,
+  input        clear_i,
+  output [7:0] hash_o
+);
+
+  logic enable, sel, ready;
+  logic [7:0] data_in, data_out;
+
+  crc_lfsr i_lfsr (
+    .rst_ni ( rst_ni   ),
+    .clk_i  ( clk_i    ),
+    .en_i   ( enable   ),
+    .data_i ( data_in  ),
+    .data_o ( data_out )
+  );
+
+  assign data_in = sel ? (data_i ^ data_out) : 8'b00000001;
+  assign hash_o  = data_out;
+  assign ready_o = ready;
+
+  always_comb begin
+    ready = 1'b1;
+    enable = valid_i;
+    sel = 1'b1;
+    if(clear_i==1'b1) begin
+      ready = 1'b0;
+      enable = 1'b1;
+      sel = 1'b0;
+    end
+  end
+
+endmodule

ex02/sourcecode/cdc_2phase.sv

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+// Copyright 2024 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+
+module crc_lfsr (
+  input        rst_ni,
+  input        clk_i,
+  input        en_i,
+  input  [7:0] data_i,
+  output [7:0] data_o
+);
+
+  logic [7:0] data_d, data_q;
+
+  assign data_d      = data_i;
+  assign data_o[7:1] = data_q[6:0];
+  assign data_o[0]   = data_q[7] ^ (data_q[5] ^ (data_q[4] ^ data_q[3]));
+
+  always_ff @(posedge clk_i, negedge rst_ni) begin
+    if (rst_ni == 0) begin
+      data_q = 0;
+    end else begin
+      if(en_i == 1'b1) data_q = data_d;
+    end
+  end
+
+endmodule

ex02/sourcecode/crc_hasher.sv

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+// Copyright 2024 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+
+module crc_stream (
+  input        rst_ni,
+  input        clk_i,
+
+  input  [7:0] data_i,
+  input        last_i,
+  input        valid_i,
+  output       ready_o,
+
+  output [7:0] data_o,
+  output       last_o,
+  output       valid_o,
+  input        ready_i
+);
+
+  typedef enum {init, data, append} state_t;
+  state_t state_d, state_q;
+  logic lfsr_valid, lfsr_ready, lfsr_clear, out_sel;
+  logic [7:0] hash_data;
+
+  logic last_out, valid_out, ready_out;
+
+  assign last_o  = last_out;
+  assign valid_o = valid_out;
+  assign ready_o = ready_out;
+
+  crc_hasher i_hasher (
+    .rst_ni  ( rst_ni     ),
+    .clk_i   ( clk_i      ),
+    .data_i  ( data_i     ),
+    .valid_i ( lfsr_valid ),
+    .ready_o ( lfsr_ready ),
+    .clear_i ( lfsr_clear ),
+    .hash_o  ( hash_data  )
+  );
+
+  assign data_o = ~out_sel ? data_i : hash_data;
+
+  always_ff @(posedge clk_i, negedge rst_ni) begin
+    if (rst_ni == 0) begin
+      state_q = init;
+    end else begin
+      state_q = state_d;
+    end
+  end
+
+  always_comb begin
+    state_d = state_q;
+
+    lfsr_valid = 0;
+    lfsr_clear = 0;
+    out_sel = 0;
+
+    last_out = 0;
+    valid_out = 0;
+    ready_out = 0;
+
+    case(state_q)
+      init: begin
+        lfsr_clear = 1'b1;
+        state_d = data;
+      end
+
+      data: begin
+        valid_out = valid_i & ready_i & lfsr_ready;
+        lfsr_valid = valid_i & ready_i;
+        ready_out = ready_i & lfsr_ready;
+        if((valid_i & ready_i & lfsr_ready & last_i) == 1'b1) begin
+          state_d = append;
+        end
+      end
+      append: begin
+        out_sel = 1;
+        last_out = 1;
+        valid_out = 1;
+        if(ready_i == 1) begin
+          state_d = init;
+        end
+      end
+      default: begin end
+    endcase
+  end
+
+endmodule