CHIPS Alliance

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113 repositories

caliptra-web
Public
Python
•
Apache License 2.0
•6•1•0•0•Updated Mar 18, 2026Mar 18, 2026
caliptra-infra
Public
Various tools used for Caliptra's Continuous Integration flows
SystemVerilog
•
Apache License 2.0
•4•2•7•2•Updated Mar 18, 2026Mar 18, 2026
caliptra-mcu-sw
Public
Caliptra MCU Software
Rust
•
Apache License 2.0
•46•25•158•39•Updated Mar 18, 2026Mar 18, 2026
caliptra-sw
Public
Caliptra software (ROM, FMC, runtime firmware), and libraries/tools needed to build and test
Rust
•
Apache License 2.0
•94•144•205•76•Updated Mar 18, 2026Mar 18, 2026
caliptra-rtl
Public
HW Design Collateral for Caliptra RoT IP
SystemVerilog
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Apache License 2.0
•82•133•114•35•Updated Mar 18, 2026Mar 18, 2026
caliptra-dpe
Public
High level module that implements DPE and defines high-level traits that are used to communicate with the crypto peripherals and PCRs
Rust
•
Apache License 2.0
•29•21•17•10•Updated Mar 18, 2026Mar 18, 2026
caliptra-ss
Public
HW Design Collateral for Caliptra Subsystem, which comprises Caliptra RoT IP and additional manufacturer controls.
security rot ocp
security rot ocp root-of-trust caliptra opencomputeproject
SystemVerilog
•
Apache License 2.0
•37•39•66•12•Updated Mar 18, 2026Mar 18, 2026
verilator
Public
Verilator open-source SystemVerilog simulator and lint system
SystemVerilog
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Other
•776•42•0•0•Updated Mar 18, 2026Mar 18, 2026
chisel
Public
Chisel: A Modern Hardware Design Language
scala chip-generator chisel
scala chip-generator chisel rtl chisel3 firrtl verilog
Scala
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Apache License 2.0
•654•4.6k•351•147•Updated Mar 18, 2026Mar 18, 2026
i3c-core
Public
SystemVerilog
•
Apache License 2.0
•24•46•15•3•Updated Mar 18, 2026Mar 18, 2026
sv-tests
Public
Test suite designed to check compliance with the SystemVerilog standard.
rtl verilog systemverilog
rtl verilog systemverilog hdl compliance-testing symbiflow
SystemVerilog
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ISC License
•88•368•47•25•Updated Mar 17, 2026Mar 17, 2026
Caliptra
Public
Caliptra IP and firmware for integrated Root of Trust block
Apache License 2.0
•60•386•75•16•Updated Mar 17, 2026Mar 17, 2026
t1
Public
Scala
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Apache License 2.0
•45•312•19•30•Updated Mar 14, 2026Mar 14, 2026
tac
Public
CHIPS Alliance Technical Advisory Council
Apache License 2.0
•25•8•42•3•Updated Mar 13, 2026Mar 13, 2026
verible
Public
Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server
productivity parser formatter
productivity parser formatter analysis style-linter linter language-server-protocol syntax-tree lexer yacc
C++
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Other
•275•1.8k•560•30•Updated Mar 13, 2026Mar 13, 2026
sv-tests-results
Public
Output of the sv-tests runs.
HTML
•6•9•0•0•Updated Mar 12, 2026Mar 12, 2026
Cores-VeeR-EL2
Public
VeeR EL2 Core
fpga processor riscv
fpga processor riscv rtl risc-v open-source-hardware fusesoc verilator riscv32 western-digital
SystemVerilog
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Apache License 2.0
•98•322•33•9•Updated Mar 12, 2026Mar 12, 2026
adams-bridge
Public
Post-Quantum Cryptography IP Core (Crystals-Dilithium)
cryptography digital-signature lattice
cryptography digital-signature lattice pqc ml-dsa-87
SystemVerilog
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Apache License 2.0
•11•48•21•7•Updated Mar 12, 2026Mar 12, 2026
sv-tools
Public
A SystemVerilog toolchain / suite, encompassing a number of open source tools for working with SystemVerilog and UVM
Apache License 2.0
•0•1•0•0•Updated Mar 9, 2026Mar 9, 2026
Surelog
Public
SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compiles on Linux gcc, Window…
parser linter preprocessor
parser linter preprocessor antlr verilog python-api systemverilog uvm elaboration vpi
C++
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Apache License 2.0
•79•451•47•0•Updated Mar 8, 2026Mar 8, 2026
firrtl-spec
Public
The specification for the FIRRTL language
TeX
•31•63•25•18•Updated Mar 7, 2026Mar 7, 2026
riscv-dv
Public
Random instruction generator for RISC-V processor verification
Python
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Apache License 2.0
•376•1.3k•130•28•Updated Mar 5, 2026Mar 5, 2026
chips-alliance-website
Public
SCSS
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MIT License
•7•5•8•8•Updated Feb 27, 2026Feb 27, 2026
rocket-chip
Public
Rocket Chip Generator
scala rocket-chip chip-generator
scala rocket-chip chip-generator chisel riscv rtl
Scala
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Other
•1.2k•3.7k•258•67•Updated Feb 25, 2026Feb 25, 2026
chisel-template
Public template
A template project for beginning new Chisel work
Shell
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The Unlicense
•199•694•14•2•Updated Feb 24, 2026Feb 24, 2026
rocket-pcb
Public
PCB libraries and templates for rocket-chip based FPGA/ASIC designs
Verilog
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Apache License 2.0
•4•16•0•1•Updated Feb 24, 2026Feb 24, 2026
caliptra-cfi
Public
Code-flow Integrity module to mitigate glitches and fault injections
Rust
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Apache License 2.0
•4•3•2•0•Updated Feb 23, 2026Feb 23, 2026
UHDM
Public
Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, Visitor and Listener. U…
serialization listener systemverilog
serialization listener systemverilog ieee-standard vpi-api vpi-interface
C++
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Apache License 2.0
•42•252•14•0•Updated Feb 22, 2026Feb 22, 2026
firrtl-syntax
Public
TextMate-compatible description of FIRRTL syntax for use with GitHub's Linguist
Apache License 2.0
•1•3•0•0•Updated Feb 16, 2026Feb 16, 2026
guineveer
Public
https://chipsalliance.github.io/guineveer/
C
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Apache License 2.0
•3•5•0•0•Updated Feb 13, 2026Feb 13, 2026