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mhubert3/README.md

Morgan Huberty

Computer Engineering Undergraduate @ Johns Hopkins University

ECE student focused on digital hardware architecture and RTL design. I am actively building my foundation in VHDL and C/C++ while learning SystemVerilog, with a vision to leverage hardware acceleration to solve complex data bottlenecks.

⚙️ Current Focus & Exploration

  • Currently Building: Expanding my digital logic foundation and self-studying SystemVerilog.
  • Looking Forward: Researching ASIC engineering pipelines, EDA tools, and High-Level Synthesis (HLS) for massive data pipelines.
  • Interdisciplinary Interests: Exploring the intersection of custom silicon and the future of health optimization, with a specific regard for genomics. I believe biological data processing will demand unique hardware innovation.

🔬 Project Coursework & Implementations

  • Serial UART Transceiver - VHDL
    • Implemented an RS-232 serial transceiver with configurable baud rate. Interfaced with an FTDI USB-UART bridge.
  • I2C Serial Controller - VHDL
    • Implemented an I²C master featuring start/stop conditions, ACK/NACK handling, and open-drain SDA/SCL signaling.
  • Set-Associative Cache Simulator - C/C++
    • Simulated a configurable set-associative cache outputting hit/miss and cycle counts from benchmark traces.
  • Multithreaded Key/Value Store - C++
    • Built an in-memory K/V store utilizing custom message serialization and a multithreaded server with table-level locking.
  • Big Integers - C++
    • Implemented a BigInt class supporting core arithmetic, bitwise operations, and hex/dec conversions.

📬 Connect with Me

Pinned Loading

  1. FPGA-Serial-UART FPGA-Serial-UART Public

    This repository contains a fully synthesizable RS-232 Universal Asynchronous Receiver-Transmitter (UART) implemented in VHDL. The project includes a customized FSM architecture for both the transmi…

    VHDL

  2. FPGA-Serial-I2C FPGA-Serial-I2C Public

    This project implements an I²C master controller. It features precise finite state machine control to manage start/stop conditions, ACK/NACK handling, and dynamic open-drain SDA/SCL signaling. The …

    VHDL

  3. Big-Int Big-Int Public

    This project implements a custom, arbitrary-precision integer data type in C++. It features an unbounded sign-magnitude representation to bypass 64-bit hardware limits, alongside algorithms for cor…

    C++

  4. Cache-Simulator Cache-Simulator Public

    This project implements a configurable C++ cache simulator to analyze memory hierarchy performance. It features flexible parameterization to evaluate architectural trade-offs—including associativit…

    C++

  5. KeyValue-Store KeyValue-Store Public

    This project implements a multithreaded, in-memory key/value store using a C++ client-server architecture. It features a concurrent server that handles multiple client connections, utilizing mutex …

    C++