pip install fusesoc
fusesoc library add logilib https://gitlab.com/jalcim/logilibSee example/ for a complete usage example.
graphical interface ./scripts/manager/manager.py
Logilib is high density and performance logic library developped on a fully structural way. The objective is to provide a stdcell library for yosys, highly parameterizable. In option we provide a POC python (amaranth wrapper) for direct using. Its a piece of a more big environnement with a logilib/libcmos architecture on top of pdk wrapper.
The src/tensor/ directory contains a high-performance 2D convolution accelerator with:
- Zero latency - 100% combinational logic, no clock cycles
- Massive parallelism - 729 simultaneous operations for 9×9 images with 3×3 kernels
- Smart edge handling - Automatic corner/border/center pixel detection
- Pure structural Verilog - No control logic, just multipliers and adders
See src/tensor/README.md for detailed documentation.
./script/lib.sh
Synthesis of design for provide final verilog/rtlil usable
./script/yosys.shResult files are on synth/
Build of simulation by running in the root folder
./script/icarus.shResult files are on bin/
Build of synthesis by running in the root folder
make synthesisBuild of co-simulation library by running in the root folder
cmake -S. -Bbuild -GNinja && cmake --build build && ./build/cosim/Vgate-testsResult files are on build/
Set time increment on each verilator eval default 1000
Enable generation of vcd trace files
If defined compile all libraries as static
Change log level, allowed values are boost severity levels:
trace debug info warning error fatal
Set list of wire numbers to generate default 1 2 3 4 7 8 16 32
When changing you need to add corresponding macros in gate_macros.h and includes in gate_includes.h
Set list of wire numbers to generate default 2 3 4 7 8
When changing you need to comment/uncomment corresponding macros in gate_macros.h and includes in gate_includes.h