feat&fix: fix bug & support verilog flow#40
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E1PsyCongroo wants to merge 15 commits intoiscas-tis:mainfrom
Open
feat&fix: fix bug & support verilog flow#40E1PsyCongroo wants to merge 15 commits intoiscas-tis:mainfrom
E1PsyCongroo wants to merge 15 commits intoiscas-tis:mainfrom
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E1PsyCongroo
commented
Mar 30, 2026
E1PsyCongroo
commented
- fix: sync CheckerWithResult npc -> now.pc at singleInstMode
- fix: mtvec -> pc when synchronous excp occur
- fix: CheckerWithWB TLB signal conn
- fix: some CSRs rmask & wmask
- feat: add more CSRs
- feat: add sub project sv-core for verilog flow
- feat: adaptation for picorv32
- feat: adaptation for nerv
- refactor: rename CheckerWithResult to CheckerWithState
- refactor: add alias for CheckerWithResult
- docs: update README
- change B-extension inst to uppercase - unify formal config into RVConfig - add JSON config support for elaborate
- rename CheckerWithResult to CheckerWithState - add excp handle in CheckerWithWB - merge excp sign to instCommit - use ChiselEnum for PrivilegeLevel - add more useful CheckTool for instset impl - handle excp logic in LoadStore - add InstAssume Helper for svcore - use JSON config for svcore - adapt interface of CheckerWithWB(excluded csr)
- update spec core csr impl to the newest riscv spec - add csr interface for WriteBackChecker - wrap nerv with writeback interface - pass instset I/B formal verification
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