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[SYCL] PR 6 - Remove FPGA Attributes from SYCL FE #21785

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Merged
sarnex merged 3 commits into from
Apr 21, 2026
Merged

[SYCL] PR 6 - Remove FPGA Attributes from SYCL FE #21785

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0cdee46
Resolve merge conflicts
premanandrao Apr 20, 2026
0cc6403
apply clang-format
premanandrao Apr 15, 2026
2710772
Fix error
premanandrao Apr 20, 2026
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35 changes: 0 additions & 35 deletions clang/include/clang/Basic/Attr.td
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Original file line number Diff line number Diff line change
Expand Up @@ -1960,23 +1960,6 @@ def SYCLIntelNumSimdWorkItems : InheritableAttr {
let SupportsNonconformingLambdaSyntax = 1;
}

def SYCLIntelUseStallEnableClusters : InheritableAttr {
let Spellings = [CXX11<"intel","use_stall_enable_clusters">];
let LangOpts = [SilentlyIgnoreSYCLIsHost, SYCLIsDevice];
let Subjects = SubjectList<[Function], ErrorDiag>;
let Documentation = [SYCLIntelUseStallEnableClustersAttrDocs];
let SupportsNonconformingLambdaSyntax = 1;
}

def SYCLIntelSchedulerTargetFmaxMhz : InheritableAttr {
let Spellings = [CXX11<"intel", "scheduler_target_fmax_mhz">];
let Args = [ExprArgument<"Value">];
let LangOpts = [SYCLIsDevice, SilentlyIgnoreSYCLIsHost];
let Subjects = SubjectList<[Function], ErrorDiag>;
let Documentation = [SYCLIntelSchedulerTargetFmaxMhzAttrDocs];
let SupportsNonconformingLambdaSyntax = 1;
}

def SYCLIntelMaxWorkGroupSize : InheritableAttr {
let Spellings = [CXX11<"intel", "max_work_group_size">];
let Args = [ExprArgument<"XDim">,
Expand Down Expand Up @@ -2928,24 +2911,6 @@ def Mode : Attr {
let PragmaAttributeSupport = 0;
}

def SYCLIntelLoopCoalesce : StmtAttr {
let Spellings = [CXX11<"intel", "loop_coalesce">];
let Subjects = SubjectList<[ForStmt, CXXForRangeStmt, WhileStmt, DoStmt],
ErrorDiag, "'for', 'while', and 'do' statements">;
let Args = [ExprArgument<"NExpr", /*opt*/1>];
let LangOpts = [SYCLIsDevice, SilentlyIgnoreSYCLIsHost];
let Documentation = [SYCLIntelLoopCoalesceAttrDocs];
}

def SYCLIntelMaxInterleaving : StmtAttr {
let Spellings = [CXX11<"intel", "max_interleaving">];
let Subjects = SubjectList<[ForStmt, CXXForRangeStmt, WhileStmt, DoStmt],
ErrorDiag, "'for', 'while', and 'do' statements">;
let Args = [ExprArgument<"NExpr">];
let LangOpts = [SYCLIsDevice, SilentlyIgnoreSYCLIsHost];
let Documentation = [SYCLIntelMaxInterleavingAttrDocs];
}

def Naked : InheritableAttr {
let Spellings = [GCC<"naked">, Declspec<"naked">];
let Subjects = SubjectList<[Function]>;
Expand Down
166 changes: 0 additions & 166 deletions clang/include/clang/Basic/AttrDocs.td
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Expand Up @@ -3262,62 +3262,6 @@ of the kernel the attribute is applied to.
}];
}

def SYCLIntelUseStallEnableClustersAttrDocs : Documentation {
let Category = DocCatFunction;
let Heading = "intel::use_stall_enable_clusters";
let Content = [{
The ``intel::use_stall_enable_clusters`` attribute requires SYCL.
When applied to a lambda function, function definition, or function call
operator (of a function object) on device, this requests, to the
extent possible, that statically-scheduled clusters handle stalls using a
stall-enable signal to freeze computation within the cluster. This attribute
is ignored on the host.

The ``intel::use_stall_enable_clusters`` attribute takes no argument and has an
effect when applied to a function, and no effect otherwise.

If ``intel::use_stall_enable_clusters`` is applied to a function called from a device
kernel, the attribute is ignored and it is not propagated to the kernel.

.. code-block:: c++

class Foo {
public:
[[intel::use_stall_enable_clusters]] void operator()() const {}
};

[[intel::use_stall_enable_clusters]] void test() {}

struct FuncObj {
[[intel::use_stall_enable_clusters]] void operator()() const {}
};

class Functor
{
[[intel::use_stall_enable_clusters]] void operator()(item<1> item)
{
/* kernel code */
}
}

The ``intel::use_stall_enable_clusters`` attribute supports a nonconforming
behavior when applied to a lambda in the type position.

.. code-block:: c++

void test1() {
auto lambda = []() [[intel::use_stall_enable_clusters]]{};
lambda();
}

kernel<class kernel_name>(
[]() [[intel::use_stall_enable_clusters]] {
/* kernel code */
});

}];
}

def ReqdWorkGroupSizeAttrDocs : Documentation {
let Category = DocCatFunction;
let Heading = "reqd_work_group_size";
Expand Down Expand Up @@ -3568,51 +3512,6 @@ have arguments of (1, 1, 1).
}];
}

def SYCLIntelSchedulerTargetFmaxMhzAttrDocs : Documentation {
let Category = DocCatFunction;
let Heading = "intel::scheduler_target_fmax_mhz";
let Content = [{
Applies to a device function/lambda function. Indicates that the kernel should
be pipelined so as to achieve the specified target clock frequency (Fmax) of N
MHz. The argument N may be a template parameter. This attribute should be
ignored for the FPGA emulator device.

``[[intel::scheduler_target_fmax_mhz(N)]]``
Valid values of N are integers in the range [0, 1048576]. The upper limit,
although too high to be a realistic value for frequency, is chosen to be future
proof. The FPGA backend emits a diagnostic message if the passed value is
unachievable by the device.

This attribute enables communication of the desired maximum frequency of the
device operation, guiding the FPGA backend to insert the appropriate number of
registers to break-up the combinational logic circuit, and thereby controlling
the length of the longest combinational path.

In SYCL 1.2.1 mode, the ``intel::scheduler_target_fmax_mhz`` attribute is
propagated from the function it is applied to onto the kernel which calls the
function. In SYCL 2020 mode, the attribute is not propagated to the kernel.

.. code-block:: c++

[[intel::scheduler_target_fmax_mhz(4)]] void foo() {}

template<int N>
[[intel::scheduler_target_fmax_mhz(N)]] void bar() {}

class Foo {
public:
[[intel::scheduler_target_fmax_mhz(6)]] void operator()() const {}
};

template <int N>
class Functor {
public:
[[intel::scheduler_target_fmax_mhz(N)]] void operator()() const {}
};

}];
}

def SYCLIntelNoGlobalWorkOffsetAttrDocs : Documentation {
let Category = DocCatFunction;
let Heading = "intel::no_global_work_offset";
Expand Down Expand Up @@ -3694,71 +3593,6 @@ sycl_detail namespace.
}];
}

def SYCLIntelLoopCoalesceAttrDocs : Documentation {
let Category = DocCatVariable;
let Heading = "intel::loop_coalesce";
let Content = [{
This attribute applies to a loop. Indicates that the loop nest should be
coalesced into a single loop without affecting functionality. Parameter N is
optional. If specified, it shall be a positive integer, and indicates how many
of the nested loop levels should be coalesced.

.. code-block:: c++

void foo() {
int a[10];
[[intel::loop_coalesce]] for (int i = 0; i != 10; ++i) a[i] = 0;
}

template<int N>
void loop_coalesce() {
int j = 0, n = 48;
[[intel::loop_coalesce(N)]]
while (j < n) {
if (j % 4) {
++j;
continue;
}
}
j = 0;
[[intel::loop_coalesce]]
while (j < n) {
if (j % 6) {
++j;
continue;
}
}
}

}];
}

def SYCLIntelMaxInterleavingAttrDocs : Documentation {
let Category = DocCatVariable;
let Heading = "intel::max_interleaving";
let Content = [{
This attribute applies to a loop. Places a maximum limit N on the number of
interleaved invocations of an inner loop by an outer loop (note, this does not
mean that this attribute can only be applied to inner loops in user code - outer
loops in user code may still be contained in an implicit loop due to NDRange).
Parameter N is mandatory, and may either be 0, or 1.

.. code-block:: c++

void foo() {
int a[10];
[[intel::max_interleaving(1)]] for (int i = 0; i != 10; ++i) a[i] = 0;
}

template<int N>
void bar() {
[[intel::max_interleaving(N)]] for(;;) { }
}

}];
}


def SYCLAddIRAttributesFunctionDocs : Documentation {
let Category = DocCatFunction;
let Heading = "add_ir_attributes_function";
Expand Down
9 changes: 0 additions & 9 deletions clang/include/clang/Sema/Sema.h
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Original file line number Diff line number Diff line change
Expand Up @@ -5208,9 +5208,6 @@ class Sema final : public SemaBase {
void ProcessDeclAttributes(Scope *S, Decl *D, const Declarator &PD);

public:

bool CheckRebuiltAttributedStmtAttributes(ArrayRef<const Attr *> Attrs);

void PopParsingDeclaration(ParsingDeclState state, Decl *decl);

/// Given a set of delayed diagnostics, re-emit them as if they had
Expand Down Expand Up @@ -11434,12 +11431,6 @@ class Sema final : public SemaBase {
Expr *E);
OpenCLUnrollHintAttr *
BuildOpenCLLoopUnrollHintAttr(const AttributeCommonInfo &A, Expr *E);

SYCLIntelMaxInterleavingAttr *
BuildSYCLIntelMaxInterleavingAttr(const AttributeCommonInfo &CI, Expr *E);
SYCLIntelLoopCoalesceAttr *
BuildSYCLIntelLoopCoalesceAttr(const AttributeCommonInfo &CI, Expr *E);

///@}

//
Expand Down
7 changes: 0 additions & 7 deletions clang/include/clang/Sema/SemaSYCL.h
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Expand Up @@ -488,10 +488,8 @@ class SemaSYCL : public SemaBase {
void handleIntelReqdSubGroupSizeAttr(Decl *D, const ParsedAttr &AL);
void handleIntelNamedSubGroupSizeAttr(Decl *D, const ParsedAttr &AL);
void handleSYCLIntelNumSimdWorkItemsAttr(Decl *D, const ParsedAttr &AL);
void handleSYCLIntelSchedulerTargetFmaxMhzAttr(Decl *D, const ParsedAttr &AL);
void handleSYCLIntelMaxGlobalWorkDimAttr(Decl *D, const ParsedAttr &AL);
void handleSYCLIntelNoGlobalWorkOffsetAttr(Decl *D, const ParsedAttr &AL);
void handleSYCLIntelUseStallEnableClustersAttr(Decl *D, const ParsedAttr &AL);
void handleIntelSimpleDualPortAttr(Decl *D, const ParsedAttr &AL);
void handleSYCLAddIRAttributesFunctionAttr(Decl *D, const ParsedAttr &AL);
void handleSYCLAddIRAttributesKernelParameterAttr(Decl *D,
Expand All @@ -514,8 +512,6 @@ class SemaSYCL : public SemaBase {
SYCLIntelNumSimdWorkItemsAttr *
mergeSYCLIntelNumSimdWorkItemsAttr(Decl *D,
const SYCLIntelNumSimdWorkItemsAttr &A);
SYCLIntelSchedulerTargetFmaxMhzAttr *mergeSYCLIntelSchedulerTargetFmaxMhzAttr(
Decl *D, const SYCLIntelSchedulerTargetFmaxMhzAttr &A);
SYCLIntelMaxGlobalWorkDimAttr *
mergeSYCLIntelMaxGlobalWorkDimAttr(Decl *D,
const SYCLIntelMaxGlobalWorkDimAttr &A);
Expand Down Expand Up @@ -609,9 +605,6 @@ class SemaSYCL : public SemaBase {
Expr **Exprs, unsigned Size);
void addSYCLIntelNumSimdWorkItemsAttr(Decl *D, const AttributeCommonInfo &CI,
Expr *E);
void addSYCLIntelSchedulerTargetFmaxMhzAttr(Decl *D,
const AttributeCommonInfo &CI,
Expr *E);
void addSYCLIntelNoGlobalWorkOffsetAttr(Decl *D,
const AttributeCommonInfo &CI,
Expr *E);
Expand Down
68 changes: 1 addition & 67 deletions clang/lib/CodeGen/CGLoopInfo.cpp
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Expand Up @@ -553,19 +553,6 @@ SmallVector<Metadata *, 4> LoopInfo::createMetadata(
LoopProperties.push_back(MDNode::get(Ctx, Vals));
}

if (Attrs.SYCLLoopCoalesceEnable) {
Metadata *Vals[] = {MDString::get(Ctx, "llvm.loop.coalesce.enable")};
LoopProperties.push_back(MDNode::get(Ctx, Vals));
}

if (Attrs.SYCLLoopCoalesceNLevels > 0) {
Metadata *Vals[] = {
MDString::get(Ctx, "llvm.loop.coalesce.count"),
ConstantAsMetadata::get(ConstantInt::get(
llvm::Type::getInt32Ty(Ctx), Attrs.SYCLLoopCoalesceNLevels))};
LoopProperties.push_back(MDNode::get(Ctx, Vals));
}

// disable_loop_pipelining attribute corresponds to
// 'llvm.loop.intel.pipelining.enable, i32 0' metadata
if (Attrs.SYCLLoopPipeliningDisable) {
Expand Down Expand Up @@ -626,8 +613,7 @@ LoopAttributes::LoopAttributes(bool IsParallel)
UnrollAndJamEnable(LoopAttributes::Unspecified),
VectorizePredicateEnable(LoopAttributes::Unspecified), VectorizeWidth(0),
VectorizeScalable(LoopAttributes::Unspecified), InterleaveCount(0),
SYCLIInterval(0), SYCLLoopCoalesceEnable(false),
SYCLLoopCoalesceNLevels(0), SYCLLoopPipeliningDisable(false),
SYCLIInterval(0), SYCLLoopPipeliningDisable(false),
SYCLLoopPipeliningEnable(false), UnrollCount(0), UnrollAndJamCount(0),
DistributeEnable(LoopAttributes::Unspecified), PipelineDisabled(false),
LICMDisabled(false), PipelineInitiationInterval(0), CodeAlign(0),
Expand All @@ -642,8 +628,6 @@ void LoopAttributes::clear() {
ArraySYCLIVDepInfo.clear();
SYCLIInterval = 0;
SYCLMaxConcurrencyNThreads.reset();
SYCLLoopCoalesceEnable = false;
SYCLLoopCoalesceNLevels = 0;
SYCLLoopPipeliningDisable = false;
SYCLMaxInterleavingNInvocations.reset();
SYCLIntelFPGAVariantCount.clear();
Expand Down Expand Up @@ -680,8 +664,6 @@ LoopInfo::LoopInfo(BasicBlock *Header, const LoopAttributes &Attrs,
Attrs.InterleaveCount == 0 && !Attrs.GlobalSYCLIVDepInfo.has_value() &&
Attrs.ArraySYCLIVDepInfo.empty() && Attrs.SYCLIInterval == 0 &&
!Attrs.SYCLMaxConcurrencyNThreads &&
Attrs.SYCLLoopCoalesceEnable == false &&
Attrs.SYCLLoopCoalesceNLevels == 0 &&
Attrs.SYCLLoopPipeliningDisable == false &&
!Attrs.SYCLMaxInterleavingNInvocations &&
Attrs.SYCLIntelFPGAVariantCount.empty() && Attrs.UnrollCount == 0 &&
Expand Down Expand Up @@ -1021,54 +1003,6 @@ void LoopInfoStack::push(BasicBlock *Header, clang::ASTContext &Ctx,
}
}

// Translate intelfpga loop attributes' arguments to equivalent Attr enums.
// It's being handled separately from LoopHintAttrs not to support
// legacy GNU attributes and pragma styles.
//
// For attribute ivdep:
// Metadata 'llvm.loop.parallel_access_indices' & index group metadata
// will be emitted, depending on the conditions described at the
// helpers' site
// For attribute ii:
// n - 'llvm.loop.ii.count, i32 n' metadata will be emitted
// For attribute max_concurrency:
// n - 'llvm.loop.max_concurrency.count, i32 n' metadata will be emitted
// For attribute loop_coalesce:
// without parameter - 'lvm.loop.coalesce.enable' metadata will be emitted
// n - 'llvm.loop.coalesce.count, i32 n' metadata will be emitted
// For attribute disable_loop_pipelining:
// 'llvm.loop.intel.pipelining.enable, i32 0' metadata will be emitted
// For attribute max_interleaving:
// n - 'llvm.loop.max_interleaving.count, i32 n' metadata will be emitted
// For attribute speculated_iterations:
// n - 'llvm.loop.intel.speculated.iterations.count, i32 n' metadata will be
// emitted
// For attribute nofusion:
// 'llvm.loop.fusion.disable' metadata will be emitted
// For attribute max_reinvocation_delay:
// n - 'llvm.loop.intel.max_reinvocation_delay.count, i32 n' metadata will be
// emitted
// For attribute enable_loop_pipelining:
// 'llvm.loop.intel.pipelining.enable, i32 1' metadata will be emitted
for (const auto *A : Attrs) {
if (const auto *SYCLIntelLoopCoalesce =
dyn_cast<SYCLIntelLoopCoalesceAttr>(A)) {
if (const auto *LCE = SYCLIntelLoopCoalesce->getNExpr()) {
const auto *CE = cast<ConstantExpr>(LCE);
llvm::APSInt ArgVal = CE->getResultAsAPSInt();
setSYCLLoopCoalesceNLevels(ArgVal.getSExtValue());
} else {
setSYCLLoopCoalesceEnable();
}
}

if (const auto *SYCLIntelMaxInterleaving =
dyn_cast<SYCLIntelMaxInterleavingAttr>(A)) {
const auto *CE = cast<ConstantExpr>(SYCLIntelMaxInterleaving->getNExpr());
llvm::APSInt ArgVal = CE->getResultAsAPSInt();
setSYCLMaxInterleavingNInvocations(ArgVal.getSExtValue());
}
}
// Identify loop attribute 'code_align' from Attrs.
// For attribute code_align:
// n - 'llvm.loop.align i32 n' metadata will be emitted.
Expand Down
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