[MSan] Use vector.reduce.or for >64-bit vector shadows on SPIR/SPIR-V targets#21757
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KornevNikita merged 5 commits intointel:syclfrom Apr 22, 2026
Merged
[MSan] Use vector.reduce.or for >64-bit vector shadows on SPIR/SPIR-V targets#21757KornevNikita merged 5 commits intointel:syclfrom
KornevNikita merged 5 commits intointel:syclfrom
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… targets When MSan instruments a load of a vector type whose total bit-width exceeds 64 (e.g. <3 x i32> = 96 bits, <4 x i32> = 128 bits), the existing shadow scalar conversion path will emit an instruction like `bitcast <3 x i32> %shadow to i96` (or wider). And i96 is only experimentally supported by GPU device. Fix: detect the SPIR/SPIR-V target and BitWidth > 64 case early emits a legal `llvm.vector.reduce.or` intrinsic that reduces to i32/i64.
jinge90
approved these changes
Apr 16, 2026
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@intel/llvm-gatekeepers please consider merging |
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Hi @intel/llvm-gatekeepers, this PR is ready to be merged. Thanks. |
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When MSan instruments a load of a vector type whose total bit-width exceeds 64 (e.g. <3 x i32> = 96 bits, <4 x i32> = 128 bits), the existing shadow scalar conversion path will emit an instruction like
bitcast <3 x i32> %shadow to i96(or wider). And i96 is only experimentally supported by GPU device.Fix: detect the SPIR/SPIR-V target and BitWidth > 64 case early emits a legal
llvm.vector.reduce.orintrinsic that reduces to i32/i64.