Hello Sameer! Great project.
I would like to propose adding to the project an option for working not with LVDS outputs, but with regular outputs in DDR mode. I came across two different FPGA boards with the HDMI connector connected to the wrong differential pair outputs. Because of this, ALTLVDS_TX cannot be used.
I was able to transfer serializer.sv to altddio_out. The work has been tested on Cyclone 10LP and MAX10.
I think this approach can also be used with the Lattice FPGA.
But the module requires output of all eight TMDS signals, and not four as now.
Hello Sameer! Great project.
I would like to propose adding to the project an option for working not with LVDS outputs, but with regular outputs in DDR mode. I came across two different FPGA boards with the HDMI connector connected to the wrong differential pair outputs. Because of this, ALTLVDS_TX cannot be used.
I was able to transfer serializer.sv to altddio_out. The work has been tested on Cyclone 10LP and MAX10.
I think this approach can also be used with the Lattice FPGA.
But the module requires output of all eight TMDS signals, and not four as now.