feat(palace): auto-size mesh, always refine ports, improve CPW defaults#111
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feat(palace): auto-size mesh, always refine ports, improve CPW defaults#111
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…rs, improve CPW port defaults - Add mesh auto_size module that scales refined_mesh_size to min conductor feature / 4 - Rework _setup_mesh_fields to always refine conductor surfaces and port boundaries (refine_near_conductor_curves flag now only controls PEC surfaces) - Default CPW port offset to length/2 (flush with conductor edge), length default 2.0 - Split palace_cpw notebook into palace_cpw_lumped and palace_cpw_waveport - Update mkdocs nav to reference the two new notebooks - Add unit tests for auto-sizing and mesh field line-collection logic
vvahidd
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Apr 18, 2026
Post PRs #111/#114, sim.mesh(preset="default") silently rescaled refined_mesh_size to min(preset, min_feature/4) whenever the user did not pass it explicitly. On a realistic CPW-via geometry this drove cloud solve time from ~3.6 min to ~25 min while barely moving S-params. Cloud benchmarks showed the default path was ~7x slower than necessary and preset tiers were no longer honest speed/accuracy steps (auto-sizing collapsed all three onto the same mesh). - sim.mesh(auto_size: bool = False, cells_per_feature: int = 2): auto-sizing is now explicit opt-in; presets use their literal refined_mesh_size; cpf default drops 4 -> 2 (cpf=4 was over-refining typical CPWs to ~51k nodes; cpf=2 matches the fine preset at ~23k while still scaling small features). - When auto_size=False and a conductor feature may be under-resolved, emit a warning suggesting auto_size=True. - Log a post-mesh summary line: "Mesh: N nodes \u00b7 M tets \u00b7 refined=X um \u00b7 max=Y um". - Warn when node count > 75,000 so slow configs are visible before cloud submission. Tests updated: pass cells_per_feature=4 explicitly where intent needs it; the generic auto-size-fires test asserts the new cpf=2 value.
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Summary
mesh/auto_sizemodule — automatically scalesrefined_mesh_sizetomin_conductor_feature / 4for the default preset_setup_mesh_fieldsto always refine conductor surface and port boundary edges (refine_near_conductor_curvesnow only controls PEC surfaces)offsettolength/2(flush with conductor edge),lengthdefault → 2.0 µmpalace_cpwnotebook intopalace_cpw_lumped(lumped ports) andpalace_cpw_waveport(wave ports)