This repository contains the final project for the course "Reti Logiche", part of the Computer Science and Engineering degree at Politecnico di Milano (2024/2025).
Teacher: Gianluca Palermo
The final grade is: 30L/30
Here the full specification of the project: pdf
The FPGA design was thoroughly tested using test cases generated by a custom C++ program (test-generator.cpp), ensuring correctness and robustness.
- Vivado 2016.4 – FPGA design and implementation tool used for hardware synthesis and simulation