This project demonstrates the use of the Opsero Ethernet FMC (OP031) and Robust Ethernet FMC (OP041). The design uses the GMII-to-RGMII IP core to connect the hard GEMs of the Zynq PS to the Ethernet FMC PHYs. The designs target both the Zynq and ZynqMP devices and are illustrated by the block diagrams below.
Important links:
- Datasheets for Ethernet FMC and Robust Ethernet FMC
- The user guide for these reference designs is hosted here: Zynq GEM for Ethernet FMC docs
- To report a bug: Report an issue.
- For technical support: Contact Opsero.
- To purchase the mezzanine card: Ethernet FMC order page.
This project is designed for version 2025.2 of the Xilinx tools (Vivado/Vitis/PetaLinux). If you are using an older version of the Xilinx tools, then refer to the release tags to find the version of this repository that matches your version of the tools.
In order to test this design on hardware, you will need the following:
- Vivado 2025.2
- Vitis 2025.2
- PetaLinux Tools 2025.2
- Ethernet FMC or Robust Ethernet FMC
- One of the target platforms listed below
- For designs containing AXI Ethernet Subsystem IP: Xilinx Soft TEMAC license
This repo contains several designs that target various supported development boards and their FMC connectors. The table below lists the target design name, the number of ports supported by the design and the FMC connector on which to connect the mezzanine card. Some of the target designs require a license to generate a bitstream with the AMD Xilinx tools.
| Target board | Target design | Ports | FMC Slot(s) | Standalone Echo Server |
PetaLinux | Vivado Edition |
IP License |
|---|---|---|---|---|---|---|---|
| PicoZed 7030 | pz_7030 |
4x | LPC | ✅ | ✅ | Standard 🆓 | - |
| ZC706 | zc706_lpc |
4x | LPC | ✅ | ✅ | Enterprise | - |
| ZedBoard | zedboard |
4x | LPC | ✅ | ✅ | Standard 🆓 | - |
| Target board | Target design | Ports | FMC Slot(s) | Standalone Echo Server |
PetaLinux | Vivado Edition |
IP License |
|---|---|---|---|---|---|---|---|
| PYNQ-ZU | pynqzu |
4x | LPC | ✅ | ✅ | Standard 🆓 | - |
| UltraZed-EG PCIe Carrier | uzeg_pci |
4x | LPC | ✅ | ✅ | Standard 🆓 | - |
| UltraZed-EV Carrier | uzev |
4x | HPC | ✅ | ✅ | Standard 🆓 | - |
| ZCU102 | zcu102_hpc0 |
4x | HPC0 | ✅ | ✅ | Enterprise | - |
| ZCU102 | zcu102_hpc1 |
3x | HPC1 | ✅ | ✅ | Enterprise | - |
| ZCU104 | zcu104 |
4x | LPC | ✅ | ✅ | Standard 🆓 | - |
| ZCU106 | zcu106_hpc0 |
4x | HPC0 | ✅ | ✅ | Standard 🆓 | - |
| ZCU111 | zcu111 |
4x | FMCP | ✅ | ✅ | Enterprise | - |
| ZCU208 | zcu208 |
4x | FMCP | ✅ | ✅ | Enterprise | - |
These reference designs can be driven by either a standalone application or within a PetaLinux environment. The repository includes all necessary scripts and code to build both environments. The table below outlines the corresponding applications available in each environment:
| Environment | Available Applications |
|---|---|
| Standalone | lwIP Echo Server |
| PetaLinux | Built-in Linux commands Additional tools: ethtool, phytool, iperf3 |
Clone the repo and change into its directory:
git clone https://github.com/fpgadeveloper/ethernet-fmc-zynq-gem.git
cd ethernet-fmc-zynq-gem
All builds are driven by build.py at the repo root, on both Windows
(git bash) and Linux. The build.sh / build.bat shim finds a suitable
Python 3 automatically (including the one bundled with the AMD tools).
Pick a target design label from the tables above (or run ./build.sh list), then run the build command for the stage(s) you want — each
command builds whatever it depends on automatically and skips anything
already built. On Windows without git bash, run the same commands from
Command Prompt or PowerShell using build.bat (e.g. build.bat xsa --target <target>).
You don't need to source the AMD tools first — the build runner finds Vivado, Vitis and PetaLinux automatically in their standard install locations and sets up the environment each stage needs. If your tools are installed somewhere non-standard and the runner can't find them, source the tool settings yourself before running the build.
./build.sh xsa --target <target>
Builds the Vitis workspace and the baremetal boot file (BOOT.BIN or
bit file, depending on the device family):
./build.sh standalone --target <target>
./build.sh petalinux --target <target>
Builds all of the above that the target supports, then gathers the boot
images into bootimages/*.zip:
./build.sh all --target <target>
./build.sh all --target all # every target in the repo
Also available: status, clean, project — see
./build.sh --help. On Windows, the PetaLinux and Yocto stages require a
Linux machine; the runner says so and prints the hand-off command. The
legacy make interface still works on Linux (each Makefile now wraps
build.sh) but is deprecated and will be removed at the next version
update.
We strongly encourage community contribution to these projects. Please make a pull request if you would like to share your work:
- if you've spotted and fixed any issues
- if you've added designs for other target platforms
Thank you to everyone who supports us!
This project was developed by Opsero Inc., a tight-knit team of FPGA experts delivering FPGA products and design services to start-ups and tech companies. Follow our blog, FPGA Developer, for news, tutorials and updates on the awesome projects we work on.