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[AIE2PS] Port scalar/cascade stream instruction selection support #957

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Merged
konstantinschwarz merged 1 commit into from
Apr 21, 2026
Merged

[AIE2PS] Port scalar/cascade stream instruction selection support #957

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67 changes: 67 additions & 0 deletions llvm/lib/Target/AIE/aie2ps/AIE2PSInstrInfo.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -247,6 +247,54 @@ unsigned AIE2PSInstrInfo::getOpCode(MachineInstr &I) const {
return isSigned ? AIE2PS::VUNPACK_mv_unpack_x_unpackSign1
: AIE2PS::VUNPACK_mv_unpack_x_unpackSign0;
}
// Cascade stream read (SCD)
case Intrinsic::aie2ps_scd_read_vec:
return AIE2PS::VMOV_alu_mv_alu_mv_scd_x;
case Intrinsic::aie2ps_scd_read_acc32:
return AIE2PS::VMOV_alu_mv_alu_mv_scd_bm;
case Intrinsic::aie2ps_scd_expand_lo:
return AIE2PS::VMOV_0_mv_scd_cm;
case Intrinsic::aie2ps_scd_expand_hi:
return AIE2PS::VMOV_1_mv_scd_cm;
case Intrinsic::aie2ps_scd_ACC2048: {
Register SrcReg = I.getOperand(3).getReg();
if (auto Src = getIConstantVRegValWithLookThrough(SrcReg, MRI)) {
unsigned SrcConstVal = Src->Value.getZExtValue();
switch (SrcConstVal) {
case 0:
return AIE2PS::VMOV_0_mv_scd_dm_imm;
case 1:
return AIE2PS::VMOV_1_mv_scd_dm_imm;
case 2:
return AIE2PS::VMOV_2;
case 3:
return AIE2PS::VMOV_3;
default:
llvm_unreachable("Unexpected SrcConstVal for SCD");
}
}
llvm_unreachable("Unexpected non-constant for SCD");
}
case Intrinsic::aie2ps_scd_expand_ACC1024:
case Intrinsic::aie2ps_scd_expand_ACC2048:
return AIE2PS::VMOV_alu_mv_alu_mv_scd_dm_reg;
case Intrinsic::aie2ps_scd_expand_ACC1024_incr:
case Intrinsic::aie2ps_scd_expand_ACC2048_incr:
return AIE2PS::VMOV_alu_mv_alu_mv_scd_dm_dyn;
// Cascade stream write (MCD)
case Intrinsic::aie2ps_mcd_write_vec:
return AIE2PS::VMOV_st_mv_mcd_x;
case Intrinsic::aie2ps_mcd_write_acc32:
return AIE2PS::VMOV_st_mv_mcd_bm;
// Scalar stream intrinsics
case Intrinsic::aie2ps_get_ss:
return AIE2PS::MOV_lda;
case Intrinsic::aie2ps_get_ss_nb:
return AIE2PS::MOV_nb_lda;
case Intrinsic::aie2ps_put_ms:
return AIE2PS::MOV_st_mMStream_tlast_reg;
case Intrinsic::aie2ps_put_ms_nb:
return AIE2PS::MOV_nb_st_mMStream_tlast_reg;
default:
llvm_unreachable("Unexpected Intrinsic ID");
}
Expand Down Expand Up @@ -1417,6 +1465,25 @@ Register AIE2PSInstrInfo::getUnpackSignCReg() const {
return AIE2PS::unpackSign0;
}

Register AIE2PSInstrInfo::getSSStatusReg() const { return AIE2PS::srSS0; }

Register AIE2PSInstrInfo::getMSStatusReg() const { return AIE2PS::srMS0; }

unsigned AIE2PSInstrInfo::getMoveToMSOpcode(MachineInstr &I,
unsigned ConstTLastVal) const {
const bool UseTLastImm = (ConstTLastVal == 0);
const unsigned IntrinsicID = cast<GIntrinsic>(I).getIntrinsicID();
switch (IntrinsicID) {
case Intrinsic::aie2ps_put_ms:
return UseTLastImm ? AIE2PS::MOV_st_mMStream_tlast_imm : AIE2PS::MOV_tlast;
case Intrinsic::aie2ps_put_ms_nb:
return UseTLastImm ? AIE2PS::MOV_nb_st_mMStream_tlast_imm
: AIE2PS::MOV_nb_tlast;
default:
llvm_unreachable("Unexpected Intrinsic ID");
}
}

unsigned AIE2PSInstrInfo::getScalarRegSize() const { return 32; }

unsigned AIE2PSInstrInfo::getBasicVecRegSize() const { return 256; }
Expand Down
4 changes: 4 additions & 0 deletions llvm/lib/Target/AIE/aie2ps/AIE2PSInstrInfo.h
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Original file line number Diff line number Diff line change
Expand Up @@ -131,6 +131,10 @@ class AIE2PSInstrInfo : public AIE2PSGenInstrInfo {
bool IsTailCall) const override;
Register getPackSignCReg() const override;
Register getUnpackSignCReg() const override;
Register getSSStatusReg() const override;
Register getMSStatusReg() const override;
unsigned getMoveToMSOpcode(MachineInstr &I,
unsigned ConstTLastVal) const override;
unsigned getCycleSeparatorOpcode() const override;
unsigned getGenericAddVectorEltOpcode() const override;
unsigned getGenericInsertVectorEltOpcode() const override;
Expand Down
105 changes: 105 additions & 0 deletions llvm/lib/Target/AIE/aie2ps/AIE2PSInstructionSelector.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -318,6 +318,8 @@ class AIE2PSInstructionSelector : public AIEBaseInstructionSelector {
unsigned Opcode);
bool selectBFP16_ADDMAC_CONF(MachineInstr &I, MachineRegisterInfo &MRI,
unsigned Opcode);
bool selectCascadeStreamInsn(MachineInstr &I, MachineRegisterInfo &MRI,
bool IsWrite);

private:
bool selectImpl(MachineInstr &I,
Expand Down Expand Up @@ -2056,6 +2058,26 @@ bool AIE2PSInstructionSelector::select(MachineInstr &I) {
return selectBFP16_ADDMAC_CONF(I, MRI, AIE2PS::VADDMAC_f_vaddmac_bfp16);
case Intrinsic::aie2ps_BFP640_BFP2560_ACC2048_bf_addmsc_conf:
return selectBFP16_ADDMAC_CONF(I, MRI, AIE2PS::VADDMSC_f_vaddmac_bfp16);
case Intrinsic::aie2ps_scd_read_vec:
case Intrinsic::aie2ps_scd_read_acc32:
case Intrinsic::aie2ps_scd_expand_lo:
case Intrinsic::aie2ps_scd_expand_hi:
case Intrinsic::aie2ps_scd_ACC2048:
case Intrinsic::aie2ps_scd_expand_ACC1024:
case Intrinsic::aie2ps_scd_expand_ACC2048:
case Intrinsic::aie2ps_scd_expand_ACC1024_incr:
case Intrinsic::aie2ps_scd_expand_ACC2048_incr:
return selectCascadeStreamInsn(I, MRI, false);
case Intrinsic::aie2ps_mcd_write_vec:
case Intrinsic::aie2ps_mcd_write_acc32:
return selectCascadeStreamInsn(I, MRI, true);
case Intrinsic::aie2ps_get_ss:
case Intrinsic::aie2ps_get_ss_nb:
return selectGetSS(I, MRI, MIB);
case Intrinsic::aie2ps_put_ms:
return selectPutMSB(I, MRI, MIB);
case Intrinsic::aie2ps_put_ms_nb:
return selectPutMSNB(I, MRI, MIB);
default:
return selectImpl(I, *CoverageInfo);
}
Expand Down Expand Up @@ -4802,6 +4824,89 @@ bool AIE2PSInstructionSelector::selectVST_FIFO(MachineInstr &I,
return false;
}

bool AIE2PSInstructionSelector::selectCascadeStreamInsn(
MachineInstr &I, MachineRegisterInfo &MRI, bool IsWrite) {
const Register CascadeReg = I.getOperand(IsWrite ? 1 : 0).getReg();
Register EnableReg = I.getOperand(I.getNumOperands() - 1).getReg();
MachineInstrBuilder CascadeMV;
const unsigned OpCode = TII.getOpCode(I);

// Helper to extract ACC1024 sub-register from an ACC2048 result.
auto ExtractACC1024 = [&]() {
auto DestMI = MIB.buildInstr(TargetOpcode::COPY, {CascadeReg}, {})
.addReg(CascadeMV->getOperand(0).getReg(), 0,
AIE2PS::sub_1024_acc_lo);
constrainOperandRegClass(*MF, TRI, MRI, TII, RBI, *DestMI,
AIE2PS::ACC1024RegClass, DestMI->getOperand(0));
};

if (IsWrite) {
CascadeMV = MIB.buildInstr(OpCode, {}, {}).addReg(CascadeReg);
} else {
auto IntrinsicID = cast<GIntrinsic>(I).getIntrinsicID();
switch (IntrinsicID) {
case Intrinsic::aie2ps_scd_expand_ACC2048: {
EnableReg = I.getOperand(I.getNumOperands() - 2).getReg();
const Register PosReg = I.getOperand(I.getNumOperands() - 1).getReg();
auto CopyPosReg = MIB.buildInstr(TargetOpcode::COPY,
{&AIE2PS::mR31_scdRegClass}, {PosReg});
if (!selectCopy(*CopyPosReg, MRI)) {
return false;
}
CascadeMV =
MIB.buildInstr(OpCode, {CascadeReg}, {}).addReg(CopyPosReg.getReg(0));
break;
}
case Intrinsic::aie2ps_scd_expand_ACC1024: {
EnableReg = I.getOperand(I.getNumOperands() - 2).getReg();
const Register PosReg = I.getOperand(I.getNumOperands() - 1).getReg();
auto CopyPosReg = MIB.buildInstr(TargetOpcode::COPY,
{&AIE2PS::mR31_scdRegClass}, {PosReg});
if (!selectCopy(*CopyPosReg, MRI)) {
return false;
}
Register DstReg = MRI.createVirtualRegister(&AIE2PS::ACC2048RegClass);
CascadeMV =
MIB.buildInstr(OpCode, {DstReg}, {}).addReg(CopyPosReg.getReg(0));
ExtractACC1024();
break;
}
case Intrinsic::aie2ps_scd_expand_ACC2048_incr: {
const Register R31 = I.getOperand(1).getReg();
EnableReg = I.getOperand(I.getNumOperands() - 2).getReg();
const Register PosPtrInReg =
I.getOperand(I.getNumOperands() - 1).getReg();
CascadeMV =
MIB.buildInstr(OpCode, {CascadeReg, R31}, {}).addReg(PosPtrInReg);
break;
}
case Intrinsic::aie2ps_scd_expand_ACC1024_incr: {
const Register R31 = I.getOperand(1).getReg();
EnableReg = I.getOperand(I.getNumOperands() - 2).getReg();
const Register PosPtrInReg =
I.getOperand(I.getNumOperands() - 1).getReg();
Register DstReg = MRI.createVirtualRegister(&AIE2PS::ACC2048RegClass);
auto CopyPosPtrInReg = MIB.buildInstr(
TargetOpcode::COPY, {&AIE2PS::mR31_scdRegClass}, {PosPtrInReg});
CascadeMV = MIB.buildInstr(OpCode, {DstReg, R31}, {})
.addReg(CopyPosPtrInReg.getReg(0));
RBI.constrainGenericRegister(R31, AIE2PS::mR31_scdRegClass, MRI);
ExtractACC1024();
break;
}
default:
CascadeMV = MIB.buildInstr(OpCode, {CascadeReg}, {});
break;
}
}
setUnsetCtrlRegister(MIB, *CascadeMV, MRI,
(IsWrite ? AIE2PS::crMCDEn : AIE2PS::crSCDEn), EnableReg,
1);

I.eraseFromParent();
return constrainSelectedInstRegOperands(*CascadeMV, TII, TRI, RBI);
}

namespace llvm {
InstructionSelector *
createAIE2PSInstructionSelector(const AIE2PSTargetMachine &TM,
Expand Down
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