All issues

Search results

Check code quality in a continuous way

Status: Open.

#74 In VLSI-EDA/PoC;

· racodond opened on Sep 20, 2024

Vivado configuration fails

Status: Open.

#73 In VLSI-EDA/PoC;

· poneill1001 opened on Aug 29, 2023

Please update link to OSVVM

Status: Open.

#72 In VLSI-EDA/PoC;

· JimLewis opened on Jun 8, 2023

CYCLONE II FPGA with TM1638 in VHDL code

Help Wanted

Status: Open.

#71 In VLSI-EDA/PoC;

· paskalthelordoffpga opened on Mar 24, 2023

Failed to configure

Status: Open.

#70 In VLSI-EDA/PoC;

· albydnc opened on Nov 1, 2022

Is this library being maintained?

Question

Status: Open.

#69 In VLSI-EDA/PoC;

· harry-commin-enclustra opened on Jul 13, 2022

GHDL VHDL -> Yosys code for BLOCKRAM (used as ROM)

Status: Open.

#68 In VLSI-EDA/PoC;

· PPlinux opened on Jan 8, 2022

Error during configuration

Status: Open.

#67 In VLSI-EDA/PoC;

· mbieker opened on Sep 14, 2020

"misc_strobegenerator" is missing

Status: Open.

#63 In VLSI-EDA/PoC;

· rhentges opened on Dec 11, 2018

configuration problem

Bug

Project: Infrastructure

Status: Open.

#62 In VLSI-EDA/PoC;

· sasamy1 opened on Oct 26, 2018

Submodules are not up-to-date

Bug

Status: Open.

#58 In VLSI-EDA/PoC;

· FranzForstmayr opened on Jul 6, 2018

fifo_dc_got.vhdl is missing

Bug

Status: Open.

#56 In VLSI-EDA/PoC;

· rhentges opened on Mar 5, 2018