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QSPI_XIP_CTRL: Fix missing default assignment for HREADYOUT in st_rw state #4162

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QSPI_XIP_CTRL: Fix missing default assignment for HREADYOUT in st_rw state #4162

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2 changes: 1 addition & 1 deletion flow/designs/src/chameleon/IPs/QSPI_XIP_CTRL.v
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Original file line number Diff line number Diff line change
Expand Up @@ -95,7 +95,7 @@ module QSPI_XIP_CTRL(
else HREADYOUT <= 1'b0;
st_rw : if(HTRANS[1] & HSEL & HREADY & c_hit) HREADYOUT <= 1'b1;
else if(HTRANS[1] & HSEL & HREADY & ~c_hit) HREADYOUT <= 1'b0;
//else HREADYOUT <= 1'b1;
else HREADYOUT <= 1'b1;
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@gemini-code-assist gemini-code-assist bot Apr 18, 2026

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medium

The case (state) statement (starting at line 90) is missing a default branch. Although the FSM state transitions are handled by a default value for nstate, the HREADYOUT signal is assigned within a clocked case block. It is a best practice in RTL design to include a default case for all control logic to ensure that signals are driven to a known safe state if the state register ever enters an undefined value (e.g., due to a glitch or SEU). For an AHB-Lite slave, the safe state for HREADYOUT is typically 1'b1 to prevent a permanent bus stall.

                            else HREADYOUT <= 1'b1;
                default :   HREADYOUT <= 1'b1;

endcase


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