v1.2.0.0

PeakRDL-regblock-vhdl v1.2.0.0

This release merges the upstream v1.2.0 changes into this VHDL port and includes several edge-case bug fixes.

⚠️ Note: this VHDL exporter is in a beta state. The 1.x version is derived from the upstream release and does not necessarily reflect this repository's stability. The project is feature-complete, unit tests pass, code coverage is good, and we're not aware of any bugs, but it has not yet been put through its paces on real-world projects. Please report any issues encountered.

Changed

• Re-licensed as LGPLv3 by @amykyta3 (#24, SystemRDL#146)

Added

• Support for OBI protocol (SystemRDL#158, SystemRDL#157)
• Support for cpuif error responses (SystemRDL#168, SystemRDL#76)
• Command line flag to copy reg_utils.vhd into the output directory (#30)

Fixed

• Fix read/write buffering edge case with external components (SystemRDL#167, SystemRDL#169)
• Fix single-bit std_logic to std_logic_vector conversion in register readback by @davekeeshan (#27)
• Fix single-bit std_logic to std_logic_vector conversion in storage-less read-only fields by @calebfletcher (#32)
• Fix read-buffered signed/fixed-point fields (44cda50)
• Fix read/write buffering in arrays of regfiles (#31)
• Fix single-bit block addressing for small external blocks (#29)

New Contributors

• @amykyta3 made their first contribution in #24
• @davekeeshan made their first contribution in #28
• @calebfletcher made their first contribution in #33

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Full Changelog: v1.1.1.0+vhdl...v1.2.0.0+vhdl

v1.1.1.0

PeakRDL-regblock-vhdl v1.1.1.0

This release merges the upstream v1.1.1 changes into this VHDL port.

⚠️ Note: this VHDL exporter is not yet ready for production. The 1.x version is derived from the upstream release and does not necessarily reflect this repository's stability. The project is feature-complete, unit tests pass, code coverage is good, and we're not aware of any bugs, but it has not yet been put through its paces on real-world projects. Please report any issues encountered.

Added

• Names for assertions (SystemRDL#151)

Changed

• Tidy up whitespace in generated package (SystemRDL#148)

Full Changelog: v1.1.0.0+vhdl...v1.1.1.0+vhdl

v1.1.0.0

PeakRDL_regblock-vhdl v1.1.0.0

This release merges the upstream v1.1.0 changes into this VHDL port.

⚠️ Note: this VHDL exporter is not yet ready for production. The 1.x version is derived from the upstream release and does not necessarily reflect this repository's stability. Code coverage is good and unit tests pass, and we're not aware of any bugs, but it has not yet been put through its paces on real-world projects. Please report any issues encountered.

Added

• Support for signed/unsigned fields (SystemRDL#140)
• Support for fixed-point ufixed/sfixed fields (SystemRDL#140)

Fixed

• GHDL issues when register has fields above the LSB (#22)

Full Changelog: v1.0.0.3+vhdl...v1.1.0.0+vhdl

v1.0.0.3

New VHDL Port of PeakRDL-regblock

This is the initial release of the VHDL port of PeakRDL-regblock v1.0.0. All features of the SystemVerilog exporter are supported. See the discussion on its relationship to the SystemVerilog exporter in the README.

⚠️ Note: this VHDL exporter is not yet ready for production. The 1.0.0.2 version is derived from the upstream release and does not reflect this repository's stability. Code coverage is good and unit tests pass, and we're not aware of any bugs, but it has not yet been put through its paces on real-world projects. Please report any issues encountered.

Changed

• Updated documentation
• Ported synthesis tests to VHDL
• avalon_mm_intf_pkg.vhd no longer needed for flat avalon interface

Full Changelog: v1.0.0...v1.0.0.3+vhdl

v1.0.0.2

New VHDL Port of PeakRDL-regblock

This is the initial release of the VHDL port of PeakRDL-regblock v1.0.0. All features of the SystemVerilog exporter are supported. See the discussion on its relationship to the SystemVerilog exporter in the README.

⚠️ Note: this VHDL exporter is not yet ready for production. The 1.0.0.2 version is derived from the upstream release and does not reflect this repository's stability. Code coverage is good and unit tests pass, and we're not aware of any bugs, but it has not yet been put through its paces on real-world projects. Please report any issues encountered.

Changed

• Deployed to PYPI

Full Changelog: v1.0.0...v1.0.0.2+vhdl

v1.0.0.1

New VHDL Port of PeakRDL-regblock

This is the initial release of the VHDL port of PeakRDL-regblock v1.0.0. All features of the SystemVerilog exporter are supported. See the discussion on its relationship to the SystemVerilog exporter in the README.

⚠️ Note: this VHDL exporter is not yet ready for production. The 1.0.0.0 version is derived from the upstream release and does not reflect this repository's stability. Code coverage is good and unit tests pass, and we're not aware of any bugs, but it has not yet been put through its paces on real-world projects. Please report any issues encountered.

Changed

• Deployed to PYPI

Full Changelog: v1.0.0...v1.0.0.1+vhdl

v1.0.0.0

New VHDL Port of PeakRDL-regblock

This is the initial release of the VHDL port of PeakRDL-regblock v1.0.0. All features of the SystemVerilog exporter are supported. See the discussion on its relationship to the SystemVerilog exporter in the README.

⚠️ Note: this VHDL exporter is not yet ready for production. The 1.0.0.0 version is derived from the upstream release and does not reflect this repository's stability. Code coverage is good and unit tests pass, and we're not aware of any bugs, but it has not yet been put through its paces on real-world projects. Please report any issues encountered.

Full Changelog: v1.0.0...v1.0.0.0+vhdl