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fix various bugs in the x86 processor spec #9097

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8a08069
fix various bugs in the x86 processor spec
jcrussell Apr 1, 2026
a399bce
address PR feedback
jcrussell Apr 7, 2026
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5 changes: 3 additions & 2 deletions Ghidra/Processors/x86/data/languages/avx.sinc
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Original file line number Diff line number Diff line change
Expand Up @@ -1453,6 +1453,7 @@ define pcodeop vmpsadbw_avx ;
YmmReg1[128,32] = vexVVVV_YmmReg[128,32] f* m[128,32];
YmmReg1[160,32] = vexVVVV_YmmReg[160,32] f* m[160,32];
YmmReg1[192,32] = vexVVVV_YmmReg[192,32] f* m[192,32];
YmmReg1[224,32] = vexVVVV_YmmReg[224,32] f* m[224,32];
ZmmReg1 = zext(YmmReg1);
}

Expand Down Expand Up @@ -3054,9 +3055,9 @@ define pcodeop vtestps_avx ;
local val1 = YmmReg2_m256;
local val2 = YmmReg1;
local ztest = val1 & val2;
ZF = (ztest[31,1] | ztest[63,1] | ztest[95,1] | ztest[127,1] | ztest[160,1] | ztest[191,1] | ztest[224,1] | ztest[255,1]) == 0;
ZF = (ztest[31,1] | ztest[63,1] | ztest[95,1] | ztest[127,1] | ztest[159,1] | ztest[191,1] | ztest[223,1] | ztest[255,1]) == 0;
local ctest = val1 & ~val2;
CF = (ctest[31,1] | ctest[63,1] | ctest[95,1] | ctest[127,1] | ctest[160,1] | ctest[191,1] | ctest[224,1] | ctest[255,1]) == 0;
CF = (ctest[31,1] | ctest[63,1] | ctest[95,1] | ctest[127,1] | ctest[159,1] | ctest[191,1] | ctest[223,1] | ctest[255,1]) == 0;
AF = 0;
OF = 0;
PF = 0;
Expand Down
36 changes: 17 additions & 19 deletions Ghidra/Processors/x86/data/languages/avx512.sinc
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Expand Up @@ -147,9 +147,10 @@ define pcodeop vandps_avx512vl ;
:VANDPS YmmReg1^YmmOpMask32, evexV5_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & evexV5_YmmReg; byte=0x54; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
{
local tmp:32 = vandps_avx512vl( evexV5_YmmReg, YmmReg2_m256_m32bcst );
YmmResult = vandps_avx512vl( evexV5_YmmReg, YmmReg2_m256_m32bcst );
YmmMask = YmmReg1;
build YmmOpMask32;

ZmmReg1 = zext(YmmResult);
}

Expand Down Expand Up @@ -1545,7 +1546,7 @@ define pcodeop vmovdqu64_avx512f ;
local src1 = evexV5_XmmReg[64,64];
local src2 = XmmReg2[64,64];
XmmReg1[0,64] = src2;
XmmReg1[64,64] = src2;
XmmReg1[64,64] = src1;
ZmmReg1 = zext(XmmReg1);
}

Expand All @@ -1556,7 +1557,7 @@ define pcodeop vmovhpd_avx512f ;
{
local src1 = evexV5_XmmReg[0,64];
local src2 = m64[0,64];
XmmReg1[0,64] = src2;
XmmReg1[0,64] = src1;
XmmReg1[64,64] = src2;
ZmmReg1 = zext(XmmReg1);
}
Expand Down Expand Up @@ -5486,10 +5487,11 @@ define pcodeop vpsubsw_avx512vl ;
}

# PSUBSB/PSUBSW 4-480 PAGE 1600 LINE 83302
define pcodeop psubsw_avx512bw ;
:PSUBSW ZmmReg1^ZmmOpMask16, evexV5_ZmmReg, ZmmReg2_m512 is $(VEX_NDS) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_ZmmReg; byte=0xE9; (ZmmReg1 & ZmmOpMask16) ... & ZmmReg2_m512
define pcodeop vpsubsw_avx512bw ;
:VPSUBSW ZmmReg1^ZmmOpMask16, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_ZmmReg; byte=0xE9; (ZmmReg1 & ZmmOpMask16) ... & ZmmReg2_m512
{
ZmmReg1 = psubsw_avx512bw( evexV5_ZmmReg, ZmmReg2_m512 );
ZmmResult = vpsubsw_avx512bw( evexV5_ZmmReg, ZmmReg2_m512 );
ZmmMask = ZmmReg1;
build ZmmOpMask16;
ZmmReg1 = ZmmResult;
}
Expand Down Expand Up @@ -6119,19 +6121,15 @@ define pcodeop vucomisd_avx512f ;
:VUCOMISD XmmReg1, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1); byte=0x2E; (XmmReg1 & ZmmReg1) ... & XmmReg2_m64
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)
{
local tmp:16 = vucomisd_avx512f( XmmReg2_m64 );
ZmmReg1 = zext(tmp);
# TODO set flags AF, CF, OF, PF, SF, ZF
fucompe(XmmReg1[0,64], XmmReg2_m64[0,64]);
}

# UCOMISS 4-685 PAGE 1805 LINE 93507
define pcodeop vucomiss_avx512f ;
:VUCOMISS XmmReg1, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0); byte=0x2E; (XmmReg1 & ZmmReg1) ... & XmmReg2_m32
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)
{
local tmp:16 = vucomiss_avx512f( XmmReg2_m32 );
ZmmReg1 = zext(tmp);
# TODO set flags AF, CF, OF, PF, SF, ZF
fucompe(XmmReg1[0,32], XmmReg2_m32[0,32]);
}

# UNPCKHPD 4-688 PAGE 1808 LINE 93629
Expand Down Expand Up @@ -9330,18 +9328,18 @@ define pcodeop vfpclassps_avx512dq ;

# VFPCLASSSD 5-247 PAGE 2071 LINE 106722
define pcodeop vfpclasssd_avx512dq ;
:VFPCLASSSD KReg_reg AVXOpMask, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & AVXOpMask; byte=0x67; KReg_reg ... & XmmReg2_m64
:VFPCLASSSD KReg_reg AVXOpMask, XmmReg2_m64, imm8 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & AVXOpMask; byte=0x67; KReg_reg ... & XmmReg2_m64; imm8
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)
{
KReg_reg = vfpclasssd_avx512dq( XmmReg2_m64, AVXOpMask );
KReg_reg = vfpclasssd_avx512dq( XmmReg2_m64, AVXOpMask, imm8:1 );
}

# VFPCLASSSS 5-249 PAGE 2073 LINE 106810
define pcodeop vfpclassss_avx512dq ;
:VFPCLASSSS KReg_reg AVXOpMask, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & AVXOpMask; byte=0x67; KReg_reg ... & XmmReg2_m32
:VFPCLASSSS KReg_reg AVXOpMask, XmmReg2_m32, imm8 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & AVXOpMask; byte=0x67; KReg_reg ... & XmmReg2_m32; imm8
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)
{
KReg_reg = vfpclassss_avx512dq( XmmReg2_m32, AVXOpMask );
KReg_reg = vfpclassss_avx512dq( XmmReg2_m32, AVXOpMask, imm8:1 );
}

# VGATHERDPS/VGATHERDPD 5-261 PAGE 2085 LINE 107357
Expand Down Expand Up @@ -12782,10 +12780,10 @@ define pcodeop vrangesd_avx512dq ;

# VRANGESS 5-482 PAGE 2306 LINE 118473
define pcodeop vrangess_avx512dq ;
:VRANGESS XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & evexV5_XmmReg; byte=0x51; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m32
:VRANGESS XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m32, imm8 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & evexV5_XmmReg; byte=0x51; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m32; imm8
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)
{
XmmResult = vrangess_avx512dq( evexV5_XmmReg, XmmReg2_m32 );
XmmResult = vrangess_avx512dq( evexV5_XmmReg, XmmReg2_m32, imm8:1 );
XmmMask = XmmReg1;
build XmmOpMask32;
ZmmReg1 = zext(XmmResult);
Expand Down
4 changes: 2 additions & 2 deletions Ghidra/Processors/x86/data/languages/cet.sinc
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Expand Up @@ -50,7 +50,7 @@ define pcodeop writeToUserShadowStack;
writeToShadowStack(rm32, Reg32);
}
@ifdef IA64
:WRSSQ rm64,Reg64 is $(LONGMODE_ON) & vexMode=0 & $(REX_W) & byte=0x0f; byte=0x0f; byte=0x38; byte=0xf6; rm64 & Reg64 ... {
:WRSSQ rm64,Reg64 is $(LONGMODE_ON) & vexMode=0 & $(REX_W) & byte=0x0f; byte=0x38; byte=0xf6; rm64 & Reg64 ... {
writeToShadowStack(rm64, Reg64);
}
@endif
Expand All @@ -59,7 +59,7 @@ define pcodeop writeToUserShadowStack;
writeToUserShadowStack(rm32, Reg32);
}
@ifdef IA64
:WRUSSQ rm64,Reg64 is $(LONGMODE_ON) & vexMode=0 & $(PRE_66) & $(REX_W) & byte=0x0f; byte=0x0f; byte=0x38; byte=0xf5; rm64 & Reg64 ... {
:WRUSSQ rm64,Reg64 is $(LONGMODE_ON) & vexMode=0 & $(PRE_66) & $(REX_W) & byte=0x0f; byte=0x38; byte=0xf5; rm64 & Reg64 ... {
writeToUserShadowStack(rm64, Reg64);
}
@endif
Expand Down
8 changes: 4 additions & 4 deletions Ghidra/Processors/x86/data/languages/fma.sinc
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Expand Up @@ -87,7 +87,7 @@ define pcodeop vfmadd231ps_fma ;

# VFIXUPIMMSS 5-127 PAGE 1951 LINE 101587
# WARNING: did not recognize VEX field 0 for "VFMADD231PS ymm1, ymm2, ymm3/m256"
:VFMADD231PS YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & vexVVVV_YmmReg; byte=0xB8; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256
:VFMADD231PS YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_YmmReg; byte=0xB8; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256
{
local tmp:16 = vfmadd231ps_fma( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 );
ZmmReg1 = zext(tmp);
Expand Down Expand Up @@ -406,7 +406,7 @@ define pcodeop vfmsub231ps_fma ;

# VFMSUB132PS/VFMSUB213PS/VFMSUB231PS 5-186 PAGE 2010 LINE 104394
# WARNING: did not recognize VEX field 0 for "VFMSUB231PS ymm1, ymm2, ymm3/m256"
:VFMSUB231PS YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & vexVVVV_YmmReg; byte=0xBA; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256
:VFMSUB231PS YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_YmmReg; byte=0xBA; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256
{
local tmp:16 = vfmsub231ps_fma( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 );
ZmmReg1 = zext(tmp);
Expand Down Expand Up @@ -545,7 +545,7 @@ define pcodeop vfnmadd231ps_fma ;

# VFNMADD132PS/VFNMADD213PS/VFNMADD231PS 5-206 PAGE 2030 LINE 105462
# WARNING: did not recognize VEX field 0 for "VFNMADD231PS ymm1, ymm2, ymm3/m256"
:VFNMADD231PS YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & vexVVVV_YmmReg; byte=0xBC; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256
:VFNMADD231PS YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_YmmReg; byte=0xBC; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256
{
local tmp:16 = vfnmadd231ps_fma( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 );
ZmmReg1 = zext(tmp);
Expand Down Expand Up @@ -684,7 +684,7 @@ define pcodeop vfnmsub231ps_fma ;

# VFNMSUB132PS/VFNMSUB213PS/VFNMSUB231PS 5-224 PAGE 2048 LINE 106502
# WARNING: did not recognize VEX field 0 for "VFNMSUB231PS ymm1, ymm2, ymm3/m256"
:VFNMSUB231PS YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & vexVVVV_YmmReg; byte=0xBE; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256
:VFNMSUB231PS YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_YmmReg; byte=0xBE; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256
{
local tmp:16 = vfnmsub231ps_fma( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 );
ZmmReg1 = zext(tmp);
Expand Down
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