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AArch64: propagate zero when Rs=zr in LSE instructions#9079

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liamwhite:sleigh-aarch64-lse-rs-as-zr
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AArch64: propagate zero when Rs=zr in LSE instructions#9079
liamwhite wants to merge 1 commit intoNationalSecurityAgency:masterfrom
liamwhite:sleigh-aarch64-lse-rs-as-zr

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Fixes #9017. Straightforward swap of aa_Ws to Rs_GPR32 / aa_Xs to Rs_GPR64 which already sets zero when the register is wzr/xzr

@GhidorahRex GhidorahRex self-assigned this Mar 30, 2026
@GhidorahRex GhidorahRex added Type: Bug Something isn't working Feature: Processor/AARCH64 Status: Triage Information is being gathered labels Mar 30, 2026
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You don't need to include both aa_Ws and Rs_GPR32 - especially for the subconstructors where aa_Ws is no longer being used in the subconstructor.

For swp, you would want to also replace aa_Ws in the operand print piece, and remove it from the bitpattern section since it's now redundant.

@liamwhite liamwhite force-pushed the sleigh-aarch64-lse-rs-as-zr branch from 3087dae to 1529a6d Compare April 1, 2026 13:19
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Updated

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Feature: Processor/AARCH64 Status: Triage Information is being gathered Type: Bug Something isn't working

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ARM64 SWP instruction with xzr Xs has wrong decompiler semantics

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