changes done by jc-efactory: #72 updated

[josch-a]

capacitor integrated, a 10mm SMD electrolitic footprint to test fix for issue #68, update to Kicad V9, rerouting, like the 3V3 plane was removed, now a GND layer as well and had to change a couple of capacitor to be able to fit the changes without any major redesign.

deleted .history folder

[pasrom]

Failed due to a KiCad version mismatch: KiBot requires v8, but we're on v9. Should I investigate?
@josch-a, would it be alright to push directly to this branch?
Edit: I've opened a separate PR to update KiBot to v9: #75

[martinjaeger]

@josch-a I merged @pasrom 's fix. Could you update the PR once again, please, so that we can see the diff?

I will try to do a detailed review today in the evening or latest on Friday.

[pasrom]

Heads up: once this PR is rebased on the updated main (with the KiBot v9 action from #75), the checks workflow will fail with two types of issues on the USB-C connector J3:

3 ERC errors — unconnected pins:

• Pin A4 (VBUS)
• Pin A8 (SBU1)
• Pin B8 (SBU2)

7 DRC errors — hole clearance violations on NPTH pads:

• Board setup constraint: 0.2000 mm, actual: 0.1910–0.1944 mm

I reproduced this in a separate CI run.

These might be pre-existing issues that KiCad v9 now reports more strictly. Two options:

1. Fix in the design (recommended) — connect/mark the unconnected pins and adjust the clearances
2. Add filters to checks.kibot.yaml — to suppress these known issues, assuming they are not real errors. Here's the commit that adds the filters:

    # ERC: unconnected USB-C pins on J3
    - filter: "Ignore unconnected USB-C pins on J3"
      error: 'pin_not_connected'
      regex: "Pin not connected"
    # DRC: hole clearance on J3 NPTH pads
    - filter: "Ignore hole clearance violations on USB-C connector J3"
      error: 'hole_clearance'
      regex: "Hole clearance violation.*"

Note that these filters are fairly broad — ideally they'd be scoped to J3 only, but KiBot's filter regex only matches the error description, not the component reference.

[github-actions]

Diff between main (4d6dd56) and main (25c19bd):

• bms-c1-diff_sch.pdf
• bms-c1-diff_pcb.pdf

[josch-a]

Heads up: once this PR is rebased on the updated main (with the KiBot v9 action from #75), the checks workflow will fail with two types of issues on the USB-C connector J3:

3 ERC errors — unconnected pins:

• Pin A4 (VBUS)
• Pin A8 (SBU1)
• Pin B8 (SBU2)

7 DRC errors — hole clearance violations on NPTH pads:

• Board setup constraint: 0.2000 mm, actual: 0.1910–0.1944 mm

I reproduced this in a separate CI run.

These might be pre-existing issues that KiCad v9 now reports more strictly. Two options:

1. Fix in the design (recommended) — connect/mark the unconnected pins and adjust the clearances
2. Add filters to checks.kibot.yaml — to suppress these known issues, assuming they are not real errors. Here's the commit that adds the filters:

    # ERC: unconnected USB-C pins on J3
    - filter: "Ignore unconnected USB-C pins on J3"
      error: 'pin_not_connected'
      regex: "Pin not connected"
    # DRC: hole clearance on J3 NPTH pads
    - filter: "Ignore hole clearance violations on USB-C connector J3"
      error: 'hole_clearance'
      regex: "Hole clearance violation.*"

Note that these filters are fairly broad — ideally they'd be scoped to J3 only, but KiBot's filter regex only matches the error description, not the component reference.

thanks @pasrom for heads up. I have updated as proposed. I believe they have been different in the previous version by Martin. Might have been introduce by standard setups on Joao's machine. @martinjaeger I will update the PR

[josch-a]

@martinjaeger should be ready for review now

[martinjaeger]

The changes look good. Thanks a lot @josch-a and @jc-efactory.

We just need to update the version number of the PCB. I will merge and then do that in main.