Add design rule for plated slot width validation - #7
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* Expand README with hardware, build, and enclosure details Replaces the one-line description with a standard project README: overview, hardware summary, repo layout, CI workflow rundown, enclosure pointer, and license. Includes a TODO placeholder for a PCB render URL once the build-images artifact is published. https://claude.ai/code/session_011Mt2xiQHKvSeekri8G1S4w * Add firmware section to README * Note rev A status in README * Add Rev B render gallery, encoder note, ZMK config link, anything case - Replace TODO PCB-render placeholder with top 3/4 hero - Add Renders section: top/bottom 3/4 + straight, 1x2 panel - Update Status to Rev B with matrix-bug caveat - Note encoder footprint not yet populated/tested - Link both Cimos/qmk_config and Cimos/zmk-config in Firmware - Swap enclosure: v44 case -> 2-Key Case + Anything Case --------- Co-authored-by: Claude <noreply@anthropic.com>
Co-authored-by: Claude <noreply@anthropic.com>
Co-authored-by: Claude <noreply@anthropic.com>
Enforces JLCPCB's 0.5mm minimum plated slot width. The condition matches plated through-hole pads whose X and Y hole dimensions differ (i.e. slots), and constrains the smaller dimension via the hole_size minimum.
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Summary
Implemented a new KiCad design rule to enforce minimum plated slot width requirements based on JLCPCB manufacturing specifications.
Key Changes
Hole_Size_X != Hole_Size_Yto identify slots (as opposed to circular holes)Implementation Details
The rule uses the following conditions:
This ensures that any plated slots in the design meet the 0.5mm minimum width requirement specified by the PCB manufacturer.
https://claude.ai/code/session_019BbMFKojrvbfCg1AwmH9Ne