Skip to content

T8132 smp#536

Open
yuyuyureka wants to merge 3 commits intoAsahiLinux:mainfrom
yuyuyureka:t8132-smp
Open

T8132 smp#536
yuyuyureka wants to merge 3 commits intoAsahiLinux:mainfrom
yuyuyureka:t8132-smp

Conversation

@yuyuyureka
Copy link
Copy Markdown
Contributor

@yuyuyureka yuyuyureka commented Jan 21, 2026

According to the discussion here, the RVBAR at cpu_impl_reg+0x00 is already set to the m1n1 entrypoint and locked by iBoot for all cores on M4.

Indeed, I can see the following values:

m1n1 base: 0x100034f4000
E-Cores cpu_impl_reg at 0x210X50000: 0x100100034f4001
P-Cores cpu_impl_reg at 0x211X50000: 0x1100100034f4001

And voila, when skipping the writes when the value is already correct (which previously produced SErrors when writing to the P-Core cpu_impl_reg), smp_start_secondaries() now works as expected.

@yuyuyureka yuyuyureka force-pushed the t8132-smp branch 2 times, most recently from a7d0ac2 to 40e2963 Compare January 24, 2026 08:56
Comment thread proxyclient/tools/chainload.py Outdated
Comment thread src/smp.c
Comment thread proxyclient/tools/chainload.py Outdated
@yuyuyureka yuyuyureka marked this pull request as draft February 8, 2026 19:17
Comment thread proxyclient/tools/chainload.py Outdated
Comment thread proxyclient/tools/chainload.py Outdated
@yuyuyureka
Copy link
Copy Markdown
Contributor Author

@abrender would you mind testing it again?

@xarkes
Copy link
Copy Markdown

xarkes commented Mar 12, 2026

Hello, I tried your PR on my M4 MacbookAir but I'm hitting the exception you introduced when trying to use the chainload.
After booting m1n1, here are my CPUs state:

  cpu0: [waiting] [0x210050000] = 0x10004c48000 (val: 10010004c44001)
  cpu1: [waiting] [0x210150000] = 0x10004c48000 (val: 10010004c44001)
  cpu2: [waiting] [0x210250000] = 0x10004c48000 (val: 10010004c44001)
  cpu3: [waiting] [0x210350000] = 0x10004c48000 (val: 10010004c44001)
  cpu4: [waiting] [0x210450000] = 0x10004c48000 (val: 10010004c44001)
  cpu5: [waiting] [0x210550000] = 0x10004c48000 (val: 10010004c44001)
  cpu6: [running] [0x211050000] = 0x10004c48000 (val: 110010004c44001)
  cpu7: [waiting] [0x211150000] = 0x10004c48000 (val: 110010004c44001)
  cpu8: [waiting] [0x211250000] = 0x10004c48000 (val: 110010004c44001)
  cpu9: [waiting] [0x211350000] = 0x10004c48000 (val: 110010004c44001)

According to your initial comment on the PR, it seems you have a similar state (wrong value + locked), making me think you should also raise this exception when trying to chainload.
I'm going to experiment and document myself more about it, meanwhile I'm happy to discuss on IRC.

Note: Not changing the secondary CPUs RVBARs allows me to complete the "chainload" (e.g. loading a patched m1n1), thus I'm wondering if this script should do it at all?
[EDIT]: I just understood the code, yes it does :D

Signed-off-by: Yureka <yureka@cyberchaos.dev>
@yuyuyureka
Copy link
Copy Markdown
Contributor Author

yuyuyureka commented Apr 10, 2026

I tested the following on my M4 Mac Mini:

  • Installed m1n1 using kmutil
  • The uartproxy appears
  • I can chainload m1n1 using proxyclient/tools/chainload.py

IMO this PR is ready to be merged, as it solves the problem of causing the SError in smp init (for example when chainloading).

@yuyuyureka yuyuyureka marked this pull request as ready for review April 10, 2026 07:12
Signed-off-by: Yureka <yureka@cyberchaos.dev>
Signed-off-by: Yureka <yureka@cyberchaos.dev>
@xarkes
Copy link
Copy Markdown

xarkes commented Apr 10, 2026

Tested on my M4 Macbook Air, chainloading works properly and I don't hit the Python Exception anymore.

@yuyuyureka yuyuyureka requested a review from svenpeter42 April 10, 2026 07:34
@abrender
Copy link
Copy Markdown
Contributor

@abrender would you mind testing it again?

Sorry for the delayed response - I no longer have access to the M4 to test :(

Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment

Labels

None yet

Projects

None yet

Development

Successfully merging this pull request may close these issues.

4 participants