allow declaring multiple regs within a single statement

Author: tmatos

test/verilogTests.cpp

@@ -96,14 +96,22 @@ class Testes_verilog : public CppUnit::TestFixture
       {"rbx", 32, 0},
       {"r_flag", 20, 0},
       {"r_extra_flag", 3, 0},
-      {"number_signed", 64, 1}
+      {"number_signed", 64, 1},
+      {"r_0", 1, 0},
+      {"r_1", 1, 0},
+      {"r_2", 1, 0},
+      {"r_3", 1, 0},
+      {"r_4", 1, 0},
+      {"r_5", 1, 0},
+      {"r_6", 1, 0},
+      {"r_7", 1, 0}
     };
 
     Evento* q = new_empty_event();
     Module* circuit = load_module("./verilog_sample_src/reg.v", &q);
 
     CPPUNIT_ASSERT( circuit );
-    CPPUNIT_ASSERT( circuit->listaReg.total == 12 );
+    CPPUNIT_ASSERT_EQUAL( (int)regs_info.size(), circuit->listaReg.total );
 
     for ( int i=0 ; i < circuit->listaReg.total ; i++ )
     {
@@ -281,6 +289,7 @@ class Testes_verilog : public CppUnit::TestFixture
       "./verilog_sample_src/badverilog_44.v",
       "./verilog_sample_src/badverilog_45.v",
       "./verilog_sample_src/badverilog_46.v",
+      "./verilog_sample_src/badverilog_46a.v",
       "./verilog_sample_src/badverilog_47.v",
       "./verilog_sample_src/badverilog_48.v",
       "./verilog_sample_src/badverilog_49.v",

test/verilog_sample_src/badverilog_46a.v

@@ -0,0 +1,6 @@
+
+// invalid code
+
+module bad_reg;
+  
+reg a, 

test/verilog_sample_src/reg.v

@@ -28,4 +28,8 @@ reg [EXTRA_FLAGS_END:EXTRA_FLAGS_START] r_extra_flag;
 
 reg signed [63:0] number_signed;
 
+reg r_0, r_1, r_2, r_3, r_4, r_5, r_6, r_7;
+
+// There are 20 registers in this module
+
 endmodule

verilog.c

@@ -845,9 +845,9 @@ VerilogError load_reg(Token** it, ListaToken* identifiers, ListaToken* list_para
     if (t->classe == KW_SIGNED) {
         is_signed = 1;
 
-        avanca(&t);
-        if (!t)
+        if (!avanca(&t)) {
             goto load_reg_bad_eof;
+        }
     }
 
     // range specification
@@ -869,6 +869,8 @@ VerilogError load_reg(Token** it, ListaToken* identifiers, ListaToken* list_para
         break;
     }
 
+load_reg_identifier_list:
+
     if (!isIdentificador(t)) {
         show_error_msg("Identificador nao foi encontrado",
                        t->linha, t->coluna, "um identificador", t->valor);
@@ -889,9 +891,16 @@ VerilogError load_reg(Token** it, ListaToken* identifiers, ListaToken* list_para
     if (!avanca(&t))
         goto load_reg_bad_eof;
 
+    if (t->classe == SYM_COMMA) {
+        if (!avanca(&t)) {
+            goto load_reg_bad_eof;
+        }
+        goto load_reg_identifier_list;
+    }
+
     if (t->classe != SYM_SEMICOLON) {
         show_error_msg("Simbolo esperado nao foi encontrado",
-                       t->linha, t->coluna, ";", t->valor);
+                       t->linha, t->coluna, ",' ou ';", t->valor);
         goto load_reg_bad_token;
     }