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phsauterphsauter
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treewide: improve technology portability
1 parent 59d8b0d commit da4470f

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10 files changed

+70
-61
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10 files changed

+70
-61
lines changed

‎openroad/scripts/01_floorplan.tcl‎

Lines changed: 10 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -114,8 +114,7 @@ set core_topY [lindex $coreArea 3]
114114
##########################################################################
115115
# We need to define the metal tracks
116116
# (where the wires on each metal should go)
117-
# this function is defined in init_tech.tcl
118-
makeTracks
117+
make_tracks
119118

120119
# the height of a standard cell, useful to align things
121120
set siteHeight [ord::dbu_to_microns [[dpl::get_row_site] getHeight]]
@@ -130,8 +129,8 @@ source src/instances.tcl
130129

131130
# Placing macros
132131
# use these for macro placement
133-
set floorPaddingX 20.0
134-
set floorPaddingY 20.0
132+
set floorPaddingX 10.0
133+
set floorPaddingY 10.0
135134
set floor_leftX [expr $core_leftX + $floorPaddingX]
136135
set floor_bottomY [expr $core_bottomY + $floorPaddingY]
137136
set floor_rightX [expr $core_rightX - $floorPaddingX]
@@ -148,10 +147,14 @@ placeInstance $bank0_sram0 $X $Y R0
148147

149148
# Bank1
150149
set X [expr $X]
151-
set Y [expr $Y - $RamSize256x64_H - 15]
152-
placeInstance $bank1_sram0 $X $Y R0
150+
set Y [expr $Y - $RamSize256x64_H - 55]
151+
placeInstance $bank1_sram0 $X $Y MX
153152

154-
cut_rows -halo_width_x 2 -halo_width_y 1
153+
# defined in init_tech.tcl
154+
insertTapCells
155+
156+
cut_rows -halo_width_x 1 -halo_width_y 1
157+
global_connect
155158

156159

157160
utl::report "###############################################################################"

‎openroad/scripts/02_placement.tcl‎

Lines changed: 14 additions & 19 deletions
Original file line numberDiff line numberDiff line change
@@ -30,8 +30,9 @@ source scripts/startup.tcl
3030
load_checkpoint 01_${proj_name}.floorplan
3131

3232
# Set layers used for estimate_parasitics
33-
set_wire_rc -clock -layer Metal4
34-
set_wire_rc -signal -layer Metal4
33+
setDefaultParasitics
34+
set_dont_use $dont_use_cells
35+
3536

3637
utl::report "###############################################################################"
3738
utl::report "# Stage 02: PLACEMENT"
@@ -45,11 +46,10 @@ utl::report "###################################################################
4546
# which then prevents CTS from running
4647
set clock_nets [get_nets -of_objects [get_pins -of_objects "*_reg" -filter "name == CLK"]]
4748
set_dont_touch $clock_nets
48-
set_dont_use $dont_use_cells
4949

5050
utl::report "Repair tie fanout"
51-
repair_tie_fanout sg13g2_tielo/L_LO
52-
repair_tie_fanout sg13g2_tiehi/L_HI
51+
repair_tie_fanout $tieHiPin
52+
repair_tie_fanout $tieLoPin
5353

5454
utl::report "Remove buffers"
5555
remove_buffers
@@ -61,18 +61,12 @@ save_checkpoint 02-01_${proj_name}.pre_place
6161

6262

6363
utl::report "###############################################################################"
64-
utl::report "# 02-02: GLOBAL PLACEMENT"
64+
utl::report "# 02-02: Global Placement"
6565
utl::report "###############################################################################"
6666

6767
set_thread_count 8
6868

69-
# Placement density: 60% of area occupied by standard cells
70-
set GPL_ARGS { -density 0.60 }
71-
72-
set GPL2_ARGS { -density 0.60
73-
-routability_driven
74-
-routability_check_overflow 0.30
75-
-timing_driven }
69+
# global_placement parameters:
7670
# density: In every part of the chip, about N% of the area is occupied by standard cells
7771
# routability_driven: Reduce density target when there are a lot of wires in an area
7872
# check_overflow: Higher means routability starts being considered earlier in placement
@@ -81,7 +75,7 @@ set GPL2_ARGS { -density 0.60
8175

8276
# Rough placement to get parasitics from steiner-tree estimate so we can run repair_timing
8377
utl::report "Global Placement (1)"
84-
global_placement {*}$GPL_ARGS
78+
global_placement -density 0.60
8579
report_metrics "02-02_${proj_name}.gpl1"
8680
report_image "02-02_${proj_name}.gpl1" true true
8781
save_checkpoint 02-02_${proj_name}.gpl1
@@ -98,21 +92,22 @@ save_checkpoint 02-02_${proj_name}.gpl1_repaired
9892

9993
# Actual global placement with routability and timing driven
10094
utl::report "Global Placement (2)"
101-
global_placement {*}$GPL2_ARGS
95+
global_placement -density 0.60 \
96+
-routability_driven \
97+
-routability_check_overflow 0.30 \
98+
-timing_driven
10299
report_metrics "02-02_${proj_name}.gpl2"
103100
report_image "02-02_${proj_name}.gpl2" true true
104101
save_checkpoint 02-02_${proj_name}.gpl2
105102

106103

107104
utl::report "###############################################################################"
108-
utl::report "# 02-03: DETAILED PLACEMENT"
105+
utl::report "# 02-03: Detailed Placement"
109106
utl::report "###############################################################################"
110107

111-
set DPL_ARGS {}
112-
113108
# Legalize overlapping cells
114109
utl::report "Detailed placement"
115-
detailed_placement {*}$DPL_ARGS
110+
detailed_placement
116111

117112
utl::report "Optimize mirroring"
118113
optimize_mirroring

‎openroad/scripts/03_cts.tcl‎

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -31,8 +31,9 @@ source scripts/startup.tcl
3131
load_checkpoint 02_${proj_name}.placed
3232

3333
# Set layers used for estimate_parasitics
34-
set_wire_rc -clock -layer Metal4
35-
set_wire_rc -signal -layer Metal4
34+
setDefaultParasitics
35+
set_dont_use $dont_use_cells
36+
3637

3738
utl::report "###############################################################################"
3839
utl::report "# Stage 03: CLOCK TREE SYNTHESIS"

‎openroad/scripts/04_routing.tcl‎

Lines changed: 5 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -31,24 +31,19 @@ source scripts/startup.tcl
3131
load_checkpoint 03_${proj_name}.cts
3232

3333
# Set layers used for estimate_parasitics
34-
set_wire_rc -clock -layer Metal4
35-
set_wire_rc -signal -layer Metal4
34+
setDefaultParasitics
35+
set_dont_use $dont_use_cells
36+
3637

3738
utl::report "###############################################################################"
3839
utl::report "# Stage 04: ROUTING"
3940
utl::report "###############################################################################"
4041

4142
utl::report "###############################################################################"
42-
utl::report "# 04-01: GLOBAL ROUTE"
43+
utl::report "# 04-01: Global Route"
4344
utl::report "###############################################################################"
4445

45-
# Reduce routing resources (max utilization) of lower layers by 20%
46-
# to spread routing out a bit more to other layers
47-
# OpenRoad strongly prefers routing with M2/M3 first and then when it
48-
# eventually needs M4/M5 it may struggle with finding space
49-
# to place vias down to M2/M3 -> reserve some space on M2/M3
5046
# Reduce TM1 to avoid too much routing there (bigger tracks -> bad for routing)
51-
set_global_routing_layer_adjustment Metal2-Metal3 0.20
5247
set_global_routing_layer_adjustment TopMetal1 0.20
5348
set_routing_layers -signal Metal2-TopMetal1 -clock Metal2-TopMetal1
5449

@@ -96,7 +91,7 @@ report_image "04-01_${proj_name}.grt_repaired" true true false true
9691

9792

9893
utl::report "###############################################################################"
99-
utl::report "# 04-02: DETAILED ROUTE"
94+
utl::report "# 04-02: Detailed Route"
10095
utl::report "###############################################################################"
10196

10297
# Repair antennas (requires LEF cell with class 'CORE ANTENNACELL')
@@ -106,7 +101,6 @@ repair_antennas -ratio_margin 30 -iterations 5
106101
utl::report "Detailed route"
107102
set_thread_count 8
108103
detailed_route -output_drc ${report_dir}/04_${proj_name}_route_drc.rpt \
109-
-droute_end_iter 30 \
110104
-drc_report_iter_step 5 \
111105
-save_guide_updates \
112106
-clean_patches \

‎openroad/scripts/05_finishing.tcl‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -30,8 +30,8 @@ source scripts/startup.tcl
3030
load_checkpoint 04_${proj_name}.routed
3131

3232
# Set layers used for estimate_parasitics
33-
set_wire_rc -clock -layer Metal4
34-
set_wire_rc -signal -layer Metal4
33+
setDefaultParasitics
34+
set_dont_use $dont_use_cells
3535

3636

3737
utl::report "###############################################################################"

‎openroad/scripts/init_tech.tcl‎

Lines changed: 22 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -65,24 +65,30 @@ foreach file [glob -directory $pdk_sram_lef RM_IHPSG13*.lef] {
6565
read_lef "$file"
6666
}
6767

68-
set ctsBuf [ list sg13g2_buf_16 sg13g2_buf_8 sg13g2_buf_4 sg13g2_buf_2 ]
69-
set ctsBufRoot sg13g2_buf_8
68+
# Set layers used for estimate_parasitics
69+
proc setDefaultParasitics {} {
70+
set_wire_rc -clock -layer Metal3
71+
set_wire_rc -signal -layer Metal3
72+
}
73+
74+
# Tie cell pins
75+
set tieHiPin "TIEHI/Y"
76+
set tieLoPin "TIELO/Y"
77+
78+
# Tap cell insertion
79+
proc insertTapCells {} {
80+
# no tap cells in this PDK
81+
}
7082

71-
set stdfill [ list sg13g2_fill_8 sg13g2_fill_4 sg13g2_fill_2 sg13g2_fill_1 ]
83+
set ctsBuf [ list BUFX64 BUFX32 BUFX24 BUFX16 BUFX12 BUFX8 BUFX6 BUFX4 ]
84+
set ctsBufRoot BUFX64
85+
86+
# disallow OR from inserting these cells
87+
set dont_use_cells [list sg13g2_IOPad* AOI31X*]
88+
89+
set stdfill [ list FILLER8 FILLER2 FILLER1 ]
7290

7391
set iocorner sg13g2_Corner
7492
set iofill [ list sg13g2_Filler10000 sg13g2_Filler4000 sg13g2_Filler2000 sg13g2_Filler1000 sg13g2_Filler400 sg13g2_Filler200 ]
7593

76-
# the repair_timing/repair_design commands may try to use IO cells as buffers
77-
set dont_use_cells sg13g2_IOPad*
78-
79-
proc makeTracks {} {
80-
utl::report "Metal Tracks"
81-
make_tracks Metal1 -x_offset 0 -x_pitch 0.42 -y_offset 0 -y_pitch 0.42
82-
make_tracks Metal2 -x_offset 0 -x_pitch 0.48 -y_offset 0 -y_pitch 0.48
83-
make_tracks Metal3 -x_offset 0 -x_pitch 0.42 -y_offset 0 -y_pitch 0.42
84-
make_tracks Metal4 -x_offset 0 -x_pitch 0.48 -y_offset 0 -y_pitch 0.48
85-
make_tracks Metal5 -x_offset 0 -x_pitch 0.42 -y_offset 0 -y_pitch 0.42
86-
make_tracks TopMetal1 -x_offset 1.64 -x_pitch 2.28 -y_offset 1.64 -y_pitch 2.28
87-
make_tracks TopMetal2 -x_offset 2.00 -x_pitch 4.00 -y_offset 2.00 -y_pitch 4.00
88-
}
94+
set bondPadCell bondpad_70x70_camos5l

‎openroad/src/constraints.sdc‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -96,7 +96,7 @@ puts "JTAG..."
9696
set_input_delay -min -add_delay -clock clk_jtg [ expr $TCK_JTG * 0.10 ] [get_ports {jtag_tdi_i jtag_tms_i}]
9797
set_input_delay -max -add_delay -clock clk_jtg [ expr $TCK_JTG * 0.30 ] [get_ports {jtag_tdi_i jtag_tms_i}]
9898
set_output_delay -min -add_delay -clock clk_jtg [ expr $TCK_JTG * 0.10 ] [get_ports jtag_tdo_o]
99-
set_output_delay -max -add_delay -clock clk_jtg [ expr $TCK_JTG * 0.30 ] [get_ports jtag_tdo_o]
99+
set_output_delay -max -add_delay -clock clk_jtg [ expr $TCK_JTG * 0.20 ] [get_ports jtag_tdo_o]
100100

101101
# Reset should propagate to system domain within a clock cycle.
102102
set_input_delay -max [ expr $TCK_JTG * 0.10 ] [get_ports jtag_trst_ni]

‎openroad/src/padring.tcl‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -153,7 +153,7 @@ connect_by_abutment
153153

154154
# Bondpad as separate cell placed in OpenROAD:
155155
# place the bonding pad relative to the IO cell
156-
place_bondpad -bond bondpad_70x70 -offset {5.0 -70.0} pad_*
156+
place_bondpad -bond $bondPadCell -offset {5.0 -70.0} pad_*
157157

158158
# remove rows created by via make_io_sites as they are no longer needed
159159
remove_io_rows

‎yosys/scripts/init_tech.tcl‎

Lines changed: 11 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -43,4 +43,14 @@ set tech_cells_args [concat {*}$tech_cells_args_list]
4343
# read library files
4444
foreach file $lib_list {
4545
yosys read_liberty -lib "$file"
46-
}
46+
}
47+
48+
set dont_use_list [list AOI31X1 AOI31X2]
49+
set dont_use_args [list]
50+
51+
foreach cell $dont_use_list {
52+
#ENL function of clock gating cells do not work
53+
lappend dont_use_args [concat "-dont_use " $cell]
54+
}
55+
56+
set dont_use_args [concat {*}$dont_use_args]

‎yosys/scripts/yosys_synthesis.tcl‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -142,7 +142,7 @@ set period_ps 10000
142142
# pre-process abc file (written to tmp directory)
143143
set abc_comb_script [processAbcScript scripts/abc-opt.script]
144144
# call ABC
145-
yosys abc {*}$tech_cells_args -D $period_ps -script $abc_comb_script -constr src/abc.constr -showtmp
145+
yosys abc {*}$tech_cells_args -D $period_ps -script $abc_comb_script -constr src/abc.constr {*}$dont_use_args -showtmp
146146

147147
yosys clean -purge
148148

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