SystemRDL
Is there a specific SystemRDL syntax to specify that an array of registers would be implemented as RAM (when generating SystemVerilog with PeakRDL) #259
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Hi, Is there a specific SystemRDL syntax to specify that an array of registers would be implemented as RAM (when generating SystemVerilog with PeakRDL) ? Thanks. Martin Tanguay |
Answered by
amykyta3
Apr 9, 2025
Replies: 1 comment
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No not currently. The PeakRDL-regblock exporter generally stays within the bounds of what can be normally described with the built-in SystemRDL properties. |
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Answer selected by
amykyta3
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No not currently. The PeakRDL-regblock exporter generally stays within the bounds of what can be normally described with the built-in SystemRDL properties.
In this case I would recommend using an external
meminstance, which would break out an external interface that would allow you to connect it to a RAM. See this page for more details: https://peakrdl-regblock.readthedocs.io/en/latest/rdl_features/external.html