[Snippets][CPU] Check for RISC-V RVV extension in is_supported_isa (#34993)

### Details:
Check if RVV extension is actually present on target device before
enabling snippets transformations

### Tickets:
 - N/A

### AI Assistance:
 - *AI assistance used: yes*
- The implementation is generate, manually adjusted after that and
checked on the emulator

Author: aobolensk

src/plugins/intel_cpu/src/nodes/subgraph.cpp

@@ -68,6 +68,7 @@
 
 #    include "emitters/snippets/riscv64/cpu_generator.hpp"
 #    include "executors/riscv64/subgraph.hpp"
+#    include "openvino/core/except.hpp"
 #else
 #    include "emitters/snippets/cpu_runtime_configurator.hpp"
 #    include "snippets/lowered/pass/insert_perf_count_verbose.hpp"
@@ -218,7 +219,9 @@ static _ov_dnnl_cpu_isa getHostIsa() {
 #elif defined(OPENVINO_ARCH_ARM64)
     return dnnl::impl::cpu::aarch64::asimd;
 #elif defined(OPENVINO_ARCH_RISCV64)
-    return static_cast<_ov_dnnl_cpu_isa>(ov::intel_cpu::riscv64::gv);
+    OPENVINO_ASSERT(ov::intel_cpu::riscv64::mayiuse(ov::intel_cpu::riscv64::gv),
+                    "RISC-V Subgraph code generation requires vector ISA support");
+    return ov::intel_cpu::riscv64::gv;
 #else
     OPENVINO_THROW("Subgraphs code-generator is not supported on this platform");
 #endif
@@ -319,7 +322,7 @@ void Subgraph::initSupportedPrimitiveDescriptors() {
             }
             if (lt == Blocked && shape.getRank() != 1 &&
                 (shape.getMinDims()[1] != Shape::UNDEFINED_DIM && shape.getMinDims()[1] > 1)) {
-#if defined(OPENVINO_ARCH_ARM64)
+#if defined(OPENVINO_ARCH_ARM64) || defined(OPENVINO_ARCH_RISCV64)
                 size_t blockSize = 16;
 #else
                 size_t blockSize = dnnl::impl::cpu::x64::mayiuse(dnnl::impl::cpu::x64::avx512_core) ? 16 : 8;
@@ -393,6 +396,10 @@ void Subgraph::initSupportedPrimitiveDescriptors() {
         if (dnnl::impl::cpu::aarch64::mayiuse(dnnl::impl::cpu::aarch64::asimd)) {
             impl_type = impl_desc_type::jit_asimd;
         }
+#elif defined(OPENVINO_ARCH_RISCV64)
+        if (ov::intel_cpu::riscv64::mayiuse(ov::intel_cpu::riscv64::gv)) {
+            impl_type = impl_desc_type::jit_gv;
+        }
 #else
         if (dnnl::impl::cpu::x64::mayiuse(dnnl::impl::cpu::x64::avx512_core)) {
             impl_type = impl_desc_type::jit_avx512;

src/plugins/intel_cpu/src/nodes/subgraph.h

@@ -28,6 +28,8 @@
 
 #if defined(OPENVINO_ARCH_ARM64)
 #    include "cpu/aarch64/cpu_isa_traits.hpp"
+#elif defined(OPENVINO_ARCH_RISCV64)
+#    include "nodes/kernels/riscv64/cpu_isa_traits.hpp"
 #else
 #    include "cpu/x64/cpu_isa_traits.hpp"
 #endif
@@ -85,6 +87,8 @@ class Subgraph : public Node {
     // Holds ISA version used is codeGeneration target
 #if defined(OPENVINO_ARCH_ARM64)
 #    define _ov_dnnl_cpu_isa dnnl::impl::cpu::aarch64::cpu_isa_t
+#elif defined(OPENVINO_ARCH_RISCV64)
+#    define _ov_dnnl_cpu_isa ov::intel_cpu::riscv64::cpu_isa_t
 #else
 #    define _ov_dnnl_cpu_isa dnnl::impl::cpu::x64::cpu_isa_t
 #endif

src/plugins/intel_cpu/src/transformations/transformation_pipeline.cpp

@@ -1204,7 +1204,7 @@ void Transformations::MainSnippets() {
 #elif defined(OPENVINO_ARCH_ARM64)
         return dnnl::impl::cpu::aarch64::mayiuse(dnnl::impl::cpu::aarch64::asimd);
 #elif defined(OPENVINO_ARCH_RISCV64)
-        return true;  // RISC-V with Vector Extension supports snippets
+        return ov::intel_cpu::riscv64::mayiuse(ov::intel_cpu::riscv64::gv);
 #endif
         return false;
     };