spi: Add configurable parameters for chip count and data width in order to work with Xilinx

Author: nselvara

ip/communication/spi/spi_interface.vhd

@@ -34,6 +34,8 @@ entity spi_interface is
     generic (
         SPI_CLK_POLARITY: bit := '0'; -- Clock polarity
         SPI_CLK_PHASE: bit := '0'; -- Clock phase
+        SPI_CHIPS_AMOUNT: natural := 1; -- Number of SPI chips
+        DATA_WIDTH: natural := 8; -- Width of the data bus
         CONTROLLER_AND_NOT_PERIPHERAL: boolean := true;
         MSB_FIRST_AND_NOT_LSB: boolean := true;
         ENABLE_INTERNAL_CLOCK_GATING: boolean := true;
@@ -45,16 +47,16 @@ entity spi_interface is
 
         selected_chips: in std_ulogic_vector;
 
-        tx_data: in std_ulogic_vector;
+        tx_data: in std_ulogic_vector(DATA_WIDTH - 1 downto 0);
         tx_data_valid: in std_ulogic;
 
-        rx_data: out std_ulogic_vector;
+        rx_data: out std_ulogic_vector(DATA_WIDTH - 1 downto 0);
         rx_data_valid: out std_ulogic;
 
         spi_clk_out: out std_ulogic;
         serial_data_out: out std_logic;
         serial_data_in: in std_ulogic;
-        spi_chip_select_n: inout std_ulogic_vector;
+        spi_chip_select_n: inout std_ulogic_vector(SPI_CHIPS_AMOUNT - 1 downto 0);
 
         tx_is_ongoing: out std_ulogic
     );
@@ -66,6 +68,8 @@ begin
         generic map (
             SPI_CLK_POLARITY => SPI_CLK_POLARITY,
             SPI_CLK_PHASE => SPI_CLK_PHASE,
+            SPI_CHIPS_AMOUNT => SPI_CHIPS_AMOUNT,
+            DATA_WIDTH => DATA_WIDTH,
             CONTROLLER_AND_NOT_PERIPHERAL => CONTROLLER_AND_NOT_PERIPHERAL,
             MSB_FIRST_AND_NOT_LSB => MSB_FIRST_AND_NOT_LSB,
             ENABLE_INTERNAL_CLOCK_GATING => ENABLE_INTERNAL_CLOCK_GATING,
@@ -87,6 +91,7 @@ begin
         generic map (
             SPI_CLK_POLARITY => SPI_CLK_POLARITY,
             SPI_CLK_PHASE => SPI_CLK_PHASE,
+            DATA_WIDTH => DATA_WIDTH,
             MSB_FIRST_AND_NOT_LSB => MSB_FIRST_AND_NOT_LSB
         )
         port map (

ip/communication/spi/spi_rx.vhd

@@ -15,6 +15,7 @@ entity spi_rx is
     generic (
         SPI_CLK_POLARITY: bit := '0'; -- Clock polarity
         SPI_CLK_PHASE: bit := '0'; -- Clock phase
+        DATA_WIDTH: natural := 8;
         MSB_FIRST_AND_NOT_LSB: boolean := true
     );
     port (
@@ -24,16 +25,15 @@ entity spi_rx is
         serial_data_in: in std_logic;
         spi_chip_select_n: in std_ulogic;
 
-        rx_data: out std_ulogic_vector;
+        rx_data: out std_ulogic_vector(DATA_WIDTH - 1 downto 0);
         rx_data_valid: out std_ulogic
     );
-
 end entity;
 
 architecture behavioural of spi_rx is
     package spi_pkg_constrained is new work.spi_pkg
         generic map (
-            DATA_WIDTH => rx_data'length,
+            DATA_WIDTH => DATA_WIDTH,
             MSB_FIRST_AND_NOT_LSB => MSB_FIRST_AND_NOT_LSB
         );
     use spi_pkg_constrained.all;

ip/communication/spi/spi_tx.vhd

@@ -32,6 +32,8 @@ entity spi_tx is
     generic (
         SPI_CLK_POLARITY: bit := '0'; -- Clock polarity
         SPI_CLK_PHASE: bit := '0'; -- Clock phase
+        SPI_CHIPS_AMOUNT: natural := 1;
+        DATA_WIDTH: natural := 8;
         CONTROLLER_AND_NOT_PERIPHERAL: boolean := true;
         MSB_FIRST_AND_NOT_LSB: boolean := true;
         ENABLE_INTERNAL_CLOCK_GATING: boolean := true;
@@ -43,12 +45,12 @@ entity spi_tx is
 
         selected_chips: in std_ulogic_vector;
 
-        tx_data: in std_ulogic_vector;
+        tx_data: in std_ulogic_vector(DATA_WIDTH - 1 downto 0);
         tx_data_valid: in std_ulogic;
 
         spi_clk_out: out std_ulogic;
         serial_data_out: out std_logic; -- For tri-state output
-        spi_chip_select_n: inout std_ulogic_vector;
+        spi_chip_select_n: inout std_ulogic_vector(SPI_CHIPS_AMOUNT - 1 downto 0);
 
         tx_is_ongoing: out std_ulogic
     );
@@ -57,7 +59,7 @@ end entity;
 architecture behavioural of spi_tx is
     package spi_pkg_constrained is new work.spi_pkg
         generic map (
-            DATA_WIDTH => tx_data'length,
+            DATA_WIDTH => DATA_WIDTH,
             MSB_FIRST_AND_NOT_LSB => MSB_FIRST_AND_NOT_LSB
         );
     use spi_pkg_constrained.all;

ip/communication/spi/tb_spi_interface.vhd

@@ -527,6 +527,8 @@ begin
         generic map (
             SPI_CLK_POLARITY => SPI_CLK_POLARITY,
             SPI_CLK_PHASE => SPI_CLK_PHASE,
+            SPI_CHIPS_AMOUNT => CHIP_COUNT,
+            DATA_WIDTH => DATA_WIDTH,
             CONTROLLER_AND_NOT_PERIPHERAL => CONTROLLER_AND_NOT_PERIPHERAL,
             MSB_FIRST_AND_NOT_LSB => MSB_FIRST_AND_NOT_LSB,
             ENABLE_INTERNAL_CLOCK_GATING => true,

ip/communication/spi/tb_spi_rx.vhd

@@ -49,8 +49,8 @@ architecture tb of tb_spi_rx is
     -------------------------------------------------------------
     constant SPI_CLK_POLARITY: bit := '0';
     constant SPI_CLK_PHASE: bit := '0';
-    constant MSB_FIRST_AND_NOT_LSB: boolean := true;
     constant DATA_WIDTH: positive := 8;
+    constant MSB_FIRST_AND_NOT_LSB: boolean := true;
 
     package spi_pkg_constrained is new work.spi_pkg
         generic map (
@@ -65,7 +65,7 @@ architecture tb of tb_spi_rx is
     signal serial_data_in: std_logic := '0';
     signal spi_chip_select_n: std_ulogic := '1';
 
-    signal rx_data: std_ulogic_vector(data_range_t);
+    signal rx_data: std_ulogic_vector(DATA_WIDTH - 1 downto 0) := (others => '0');
     signal rx_data_valid: std_ulogic;
     -------------------------------------------------------------
 begin
@@ -103,7 +103,7 @@ begin
     checker: process
         variable random: RandomPType;
         variable current_bit_index: data_range_t;
-        variable expected_data: std_ulogic_vector(data_range_t);
+        variable expected_data: std_ulogic_vector(DATA_WIDTH - 1 downto 0);
 
         procedure wait_spi_clk_cycles(cycles: natural) is begin
             for i in 0 to cycles - 1 loop
@@ -211,7 +211,7 @@ begin
         procedure random_test is
             constant TEST_REPERTITIONS: natural := 1000;
 
-            variable random_data: std_ulogic_vector(data_range_t);
+            variable random_data: std_ulogic_vector(DATA_WIDTH - 1 downto 0);
             variable random_spi_chip_select_n: std_ulogic;
             variable spi_chip_select_n_reg: std_ulogic;
         begin
@@ -283,6 +283,7 @@ begin
         generic map (
             SPI_CLK_POLARITY => SPI_CLK_POLARITY,
             SPI_CLK_PHASE => SPI_CLK_PHASE,
+            DATA_WIDTH => DATA_WIDTH,
             MSB_FIRST_AND_NOT_LSB => MSB_FIRST_AND_NOT_LSB
         )
         port map (

ip/communication/spi/tb_spi_tx.vhd

@@ -282,6 +282,8 @@ begin
         generic map (
             SPI_CLK_POLARITY => SPI_CLK_POLARITY,
             SPI_CLK_PHASE => SPI_CLK_PHASE,
+            SPI_CHIPS_AMOUNT => CHIP_COUNT,
+            DATA_WIDTH => DATA_WIDTH,
             CONTROLLER_AND_NOT_PERIPHERAL => CONTROLLER_AND_NOT_PERIPHERAL,
             MSB_FIRST_AND_NOT_LSB => MSB_FIRST_AND_NOT_LSB,
             ENABLE_INTERNAL_CLOCK_GATING => true,