1 parent a2480a9 commit 6fecd38Copy full SHA for 6fecd38
2 files changed
src/jsilicon.v
@@ -87,7 +87,9 @@ module tt_um_Jsilicon(
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.ena(ena),
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.opcode(regfile_opcode),
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.data_in(wb_data),
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- .data_out()
+ .data_out(),
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+ .R0_out(R0),
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+ .R1_out(R1)
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);
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// ALU - CPU mode
src/regfile.v
@@ -14,11 +14,11 @@ module REG (
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// 명령어 저장
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input wire [7:0] data_in,
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// FSM, ALU 데이터 저장
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- output reg [7:0] data_out
+ output reg [7:0] data_out,
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// 디버그 포트
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- // output wire [7:0] R0_out,
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- // output wire [7:0] R1_out
+ output wire [7:0] R0_out,
+ output wire [7:0] R1_out
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reg [7:0] R0, R1;
@@ -49,7 +49,7 @@ module REG (
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end
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- // assign R0_out = R0;
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- // assign R1_out = R1;
+ assign R0_out = R0;
+ assign R1_out = R1;
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endmodule
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