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Split XDC into phys, synth timing, & impl timing
Constraints such as false_paths cannot be applied until after elaboration/synthesis, such as internal false paths. Splitting the XDC into separate files should allow some constraints to be read later than others, such as after synthesis. Edalize/fusesoc do not seem to provide a direct mechanism for this, but does allow a custom script to set the required Vivado properties. The existing XDC is split into three files, based on advice in UG949: "1 file for physical + 1 file for timing (synthesis) + 1 file for timing (implementation)." The constraints themselves have been left unchanged for now.
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‎data/impl_timing.xdc‎

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## Copyright lowRISC contributors.
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## Licensed under the Apache License, Version 2.0, see LICENSE for details.
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## SPDX-License-Identifier: Apache-2.0
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# This file is for timing constraints to be applied *after* synthesis.
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# i.e. timing constraints on internal paths.
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set_false_path -from [get_pins -of [get_cells u_sonata_system/g_hyperram.u_hyperram/u_hbmc_tl_top/u_hbmc_cmd_fifo/*storage*/*]]
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set_false_path -from [get_pins -of [get_cells u_sonata_system/g_hyperram.u_hyperram/u_hbmc_tl_top/hbmc_ufifo_inst/u_fifo/*storage*/*]]
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set_false_path -from [get_pins -of [get_cells u_sonata_system/g_hyperram.u_hyperram/u_hbmc_tl_top/hbmc_dfifo_inst/u_fifo/*storage*/*]]
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# TODO: Want some general constraints that will setup appropriate false paths
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# for all CDC prims. An attempt is below but it isn't working yet.
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#set sync_cells [get_cells -hier -filter {ORIG_REF_NAME == prim_flop_2sync}]
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#
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#foreach sync_cell $sync_cells {
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# set sync_pins [get_pins -of [get_cells -hier -regexp $sync_cell/.*u_sync_1.*]]
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# if {[info exists endpoint_sync_pins_for_false_paths]} {
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# set endpoint_sync_pins_for_false_paths $sync_pins
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# } else {
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# lappend endpoint_sync_pins_for_false_paths $sync_pins
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# }
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#}
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#
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#set_false_path -to $endpoint_sync_pins_for_false_paths
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#
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#set async_fifo_cells [get_cells -hier -filter {ORIG_REF_NAME == prim_fifo_async}]
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#
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#foreach async_fifo_cell $async_fifo_cells {
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# set async_fifo_pins [get_pins -of [get_cells -hier -regexp $async_fifo_cell/.*storage.*]]
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# if {[info exists startpoint_fifo_async_pins_for_false_paths]} {
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# set startpoint_fifo_async_pins_for_false_paths $async_fifo_pins
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# } else {
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# lappend startpoint_fifo_async_pins_for_false_paths $async_fifo_pins
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# }
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#}
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#
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#set_false_path -from $startpoint_fifo_async_pins_for_false_paths

‎data/pins_sonata.xdc‎

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@@ -2,23 +2,15 @@
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## Licensed under the Apache License, Version 2.0, see LICENSE for details.
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## SPDX-License-Identifier: Apache-2.0
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# This file is for physical constraints.
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# Using the names in the PCB design, they should match this file with a case-insensitive search:
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# https://github.com/newaetech/sonata-pcb/tree/main
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## Clocks
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create_clock -period 40.000 -name mainClk -waveform {0.000 20.000} [get_ports mainClk]
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create_clock -period 100.000 -name tck_i -waveform {0.000 50.000} [get_ports tck_i]
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set_property -dict { PACKAGE_PIN P15 IOSTANDARD LVCMOS33 } [get_ports mainClk];
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set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets tck_i]
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## Clock Domain Crossings
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set clks_sys_unbuf [get_clocks -of_objects [get_pin u_clkgen/pll/CLKOUT0]]
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set clks_usb_unbuf [get_clocks -of_objects [get_pin u_clkgen/pll/CLKOUT1]]
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## Set asynchronous clock groups
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set_clock_groups -group ${clks_sys_unbuf} -group ${clks_usb_unbuf} -group mainClk -asynchronous
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## Reset
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## PCB revision 0.3 and above
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set_property -dict { PACKAGE_PIN T5 IOSTANDARD LVCMOS33 } [get_ports {nrst}];
@@ -291,49 +283,3 @@ set_property -dict { PACKAGE_PIN J2 IOSTANDARD LVCMOS18 } [get_ports { hype
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set_property CFGBVS VCCO [current_design]
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set_property CONFIG_VOLTAGE 3.3 [current_design]
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set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
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set_false_path -to [get_ports hyperram_ckp]
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set_false_path -to [get_ports hyperram_ckn]
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set_false_path -to [get_ports hyperram_rwds]
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set_false_path -to [get_ports hyperram_dq[*]]
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# set input false path. dq[*] and rwds are supposed to
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# be fully asynchronous for the data recovery logic
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set_false_path -from [get_ports hyperram_rwds]
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set_false_path -from [get_ports hyperram_dq[*]]
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# False path for 'hb_cs_n' and 'hb_reset_n'
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set_false_path -to [get_ports hyperram_cs]
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set_false_path -to [get_ports hyperram_nrst]
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set_false_path -from [get_pins -of [get_cells u_sonata_system/g_hyperram.u_hyperram/u_hbmc_tl_top/u_hbmc_cmd_fifo/*storage*/*]]
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set_false_path -from [get_pins -of [get_cells u_sonata_system/g_hyperram.u_hyperram/u_hbmc_tl_top/hbmc_ufifo_inst/u_fifo/*storage*/*]]
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set_false_path -from [get_pins -of [get_cells u_sonata_system/g_hyperram.u_hyperram/u_hbmc_tl_top/hbmc_dfifo_inst/u_fifo/*storage*/*]]
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# TODO: Want some general constraints that will setup appropriate false paths
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# for all CDC prims. An attempt is below but it isn't working yet.
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#set sync_cells [get_cells -hier -filter {ORIG_REF_NAME == prim_flop_2sync}]
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#
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#foreach sync_cell $sync_cells {
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# set sync_pins [get_pins -of [get_cells -hier -regexp $sync_cell/.*u_sync_1.*]]
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# if {[info exists endpoint_sync_pins_for_false_paths]} {
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# set endpoint_sync_pins_for_false_paths $sync_pins
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# } else {
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# lappend endpoint_sync_pins_for_false_paths $sync_pins
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# }
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#}
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#
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#set_false_path -to $endpoint_sync_pins_for_false_paths
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#
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#set async_fifo_cells [get_cells -hier -filter {ORIG_REF_NAME == prim_fifo_async}]
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#
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#foreach async_fifo_cell $async_fifo_cells {
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# set async_fifo_pins [get_pins -of [get_cells -hier -regexp $async_fifo_cell/.*storage.*]]
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# if {[info exists startpoint_fifo_async_pins_for_false_paths]} {
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# set startpoint_fifo_async_pins_for_false_paths $async_fifo_pins
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# } else {
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# lappend startpoint_fifo_async_pins_for_false_paths $async_fifo_pins
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# }
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#}
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#
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#set_false_path -from $startpoint_fifo_async_pins_for_false_paths

‎data/synth_timing.xdc‎

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## Copyright lowRISC contributors.
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## Licensed under the Apache License, Version 2.0, see LICENSE for details.
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## SPDX-License-Identifier: Apache-2.0
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# This file is for timing constraints to be applied *before* synthesis.
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# i.e. timing constraints on top-level ports.
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## Clocks
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create_clock -period 40.000 -name mainClk -waveform {0.000 20.000} [get_ports mainClk]
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create_clock -period 100.000 -name tck_i -waveform {0.000 50.000} [get_ports tck_i]
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## Clock Domain Crossings
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set clks_sys_unbuf [get_clocks -of_objects [get_pin u_clkgen/pll/CLKOUT0]]
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set clks_usb_unbuf [get_clocks -of_objects [get_pin u_clkgen/pll/CLKOUT1]]
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## Set asynchronous clock groups
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set_clock_groups -group ${clks_sys_unbuf} -group ${clks_usb_unbuf} -group mainClk -asynchronous
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## HyperRAM
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set_false_path -to [get_ports hyperram_ckp]
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set_false_path -to [get_ports hyperram_ckn]
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set_false_path -to [get_ports hyperram_rwds]
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set_false_path -to [get_ports hyperram_dq[*]]
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# set input false path. dq[*] and rwds are supposed to
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# be fully asynchronous for the data recovery logic
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set_false_path -from [get_ports hyperram_rwds]
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set_false_path -from [get_ports hyperram_dq[*]]
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# False path for 'hb_cs_n' and 'hb_reset_n'
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set_false_path -to [get_ports hyperram_cs]
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set_false_path -to [get_ports hyperram_nrst]

‎flow/vivado_setup.tcl‎

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# Copyright lowRISC contributors.
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# Licensed under the Apache License, Version 2.0, see LICENSE for details.
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# SPDX-License-Identifier: Apache-2.0
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## Vivado project custom configuration script
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##
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## For configuration not supported by fusesoc/edalize
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# Configure when and how the post-synthesis timing XDC file is read.
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# The `Tcl` `file_type` makes Vivado use the `-unmanaged` argument with
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# `read_xdc`, which allows us to use commands such as `foreach`.
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# The `used_in_synthesis` property makes Vivado delay reading the file
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# until after synthesis, allowing internal paths to be specified.
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# Note: `file_type` must be set before `used_in_synthesis`.
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set_property file_type Tcl [get_files impl_timing.xdc]
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set_property used_in_synthesis false [get_files impl_timing.xdc]

‎sonata.core‎

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@@ -35,9 +35,16 @@ filesets:
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files_constraints_sonata:
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files:
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- data/pins_sonata.xdc
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# Per AMD advice (UG949):
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- data/pins_sonata.xdc # 1 file for physical +
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- data/synth_timing.xdc # 1 file for timing (synthesis) +
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- data/impl_timing.xdc # 1 file for timing (implementation)
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file_type: xdc
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files_tcl:
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files:
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- flow/vivado_setup.tcl : { file_type: tclSource }
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parameters:
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# XXX: This parameter needs to be absolute, or relative to the *.runs/synth_1
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# directory. It's best to pass it as absolute path when invoking fusesoc, e.g.
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filesets_append:
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- files_sonata
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- files_constraints_sonata
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- files_tcl
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toplevel: top_sonata
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tools:
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vivado:

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