Comparison between different chips/peripheral capabilities

[septatrix]

Hi, it would be great to list potential differences between the I2S, LCD, and Parlio modes of operation. I am investigating which hardware to use for a new project and being aware of those differences would be great to know.

Two aspects I can think of:

• Max clock rate, i.e. do all of them push data at the same rate as the ESP clock or use a different clock domain? This directly relates to potential bit depth one may choose
• Possibility to drive multiple panels in parallel (and not as a chain). This would allow one to trade GPIO pins for higher speeds

[liebman]

Each of those run on different chips:
i2s: esp32
lcd: esp32s3
parlio: esp32c6
All of these can handle 20-25MHz (max for most panel)
Not sure what you mean by driving panels in parrallel, if by that you mean sending the exact same image to them then sure, if you mean having seperate images in each then probably no as there is only one parallel io peripheral on most of these devices.

If you looking for efficiencies then definitely use a latch circuit as this uses less pins and less ram.

[septatrix]

Each of those run on different chips:

• i2s: esp32
• lcd: esp32s3
• parlio: esp32c6

All of these can handle 20-25MHz (max for most panel)

For example a C library for using HUB75 has discontinued ESP32-C6 support due to hardware problems: mrcodetastic/ESP32-HUB75-MatrixPanel-DMA@59bf59d

I was also looking at using a C5 which is not listed at having such problems but then I would need to use a latch circuit as its parlio peripheral only supports 8 bit wide outputs.

Not sure what you mean by driving panels in parrallel, if by that you mean sending the exact same image to them then sure, if you mean having seperate images in each then probably no as there is only one parallel io peripheral on most of these devices.

If I have a 32 row 1/16 scan panel, or a 64 row 1/32 I will always push out two sets of RGB data per clock frame. In your 2x2 example you combine four panels to effectively a 256x32 panel still pushing 2 sets of RGB data each tick. Instead, one could drive them in parallel as a "tall" 64x128 panel and push 8 sets of RGB data each tick. This makes pushing the data much quicker as they don't need to be shifted through all 4 matrices sequentially and can be shifted into each one at the same time. This obviously requires more pins but would make the drawing a lot faster.

I hope that is somewhat understandable. Otherwise I can try to make a drawing or similar to hopefully make it clearer :)

The LCD i80 mode seems to be limited to 16 bits so unlatched it would not be possible to do this, however in a 16 bit + latched setup I would be able to use that. One clock cycle for the address bits, then I can push 5 RGB pairs each subsequent tick.

There is also the RGB mode for the LCD peripheral which claims to support 24 bit mode. Have you looked at hat? Unlatched it would support 5 RGB pairs, and latched even 8 at the same time.

The I2S mode which is apparently used by some libraries even supports 32 bit output...

If you looking for efficiencies then definitely use a latch circuit as this uses less pins and less ram.

Yeah I will probably do that, it's great that you support it here :)