Discussion: Noyron SC — Computational Engineering for Semiconductor Design

[sirfyyn]

Hi Lin,

You've made the case that CAD is evil because it traps engineering knowledge in geometry rather than logic. Chips escaped that trap in the 1970s — modern chip design is computed from specs, not drawn. Verilog and VHDL are essentially what Computational Engineering already is, just for silicon.

So the question is obvious: has anyone at LEAP 71 considered applying Noyron's approach to semiconductor design — specifically processors and memory architectures?

The parallel is striking:

• Noyron RP: propellant type + thrust → manufacturable engine geometry
• Noyron SC (hypothetical): ISA + target frequency + process node → manufacturable RTL/GDSII

The EDA world is currently attacking this from the LLM direction (VeriGen, QiMeng, Synopsys AgentEngineer), but those approaches are probabilistic — they generate Verilog that might be correct. LEAP 71's approach is deterministic: physics + constraints → correct-by-construction output.

For semiconductor design specifically, that distinction matters enormously. A rocket engine you can retest. A chip tapeout costs $5–50M.

I'm curious whether this is on your roadmap, has been consciously ruled out, or whether the geometry-centric nature of PicoGK is a fundamental blocker. The output representation would be fundamentally different (planar GDSII vs. volumetric geometry), but the methodology — encoded physics, design rules, manufacturing constraints — seems directly transferable.

Would love to hear your thinking on this.