GDS may be default layout.

[d-m-bailey]

Please check that your user_project_wrapper gds is not the default layout. This is the default.

[d-m-bailey]

Looking at your user_proj_example/config.tcl file,

set ::env(VERILOG_FILES) "\
	$::env(CARAVEL_ROOT)/verilog/rtl/defines.v \
	$script_dir/../../verilog/rtl/user_proj_example.v \
	$script_dir/../../verilog/rtl/main.v"

you've included the main.v file, but the user_project_example.v file does not instantiate the main module.
I believe this means that your main module will be ignored in synthesis.

You probably want to replace the counter in user_proj_example with your main instance.