refactor(x86_64): move page tables to Rust

Author: mkroening

src/arch/x86_64/mod.rs

@@ -2,6 +2,8 @@ mod console;
 #[cfg(target_os = "none")]
 mod gdt;
 #[cfg(target_os = "none")]
+mod page_tables;
+#[cfg(target_os = "none")]
 mod physicalmem;
 mod platform;
 #[cfg(target_os = "none")]

src/arch/x86_64/page_tables.rs

@@ -0,0 +1,37 @@
+//! Page Tables.
+//!
+//! This file defines the page tables that we switch to by setting `CR3` to `LEVEL_4_TABLE`.
+
+use core::ptr;
+
+use x86_64::structures::paging::{PageSize, PageTableFlags, Size1GiB};
+
+const LEVEL_4_FLAGS: PageTableFlags = PageTableFlags::PRESENT.union(PageTableFlags::WRITABLE);
+const LEVEL_3_FLAGS: PageTableFlags = LEVEL_4_FLAGS.union(PageTableFlags::HUGE_PAGE);
+
+pub static mut LEVEL_4_TABLE: PageTable = {
+	let flags = LEVEL_4_FLAGS.bits() as usize;
+	let mut page_table = [ptr::null_mut(); _];
+
+	page_table[0] = (&raw mut LEVEL_3_TABLE).wrapping_byte_add(flags).cast();
+
+	PageTable(page_table)
+};
+
+static mut LEVEL_3_TABLE: PageTable = {
+	let flags: usize = LEVEL_3_FLAGS.bits() as usize;
+	let mut page_table = [ptr::null_mut(); _];
+
+	let mut i = 0;
+	while i < page_table.len() {
+		let addr = i * Size1GiB::SIZE as usize;
+		page_table[i] = ptr::with_exposed_provenance_mut(addr + flags);
+		i += 1;
+	}
+
+	PageTable(page_table)
+};
+
+#[repr(align(0x1000))]
+#[repr(C)]
+pub struct PageTable([*mut (); 512]);

src/arch/x86_64/platform/linux/entry.s

@@ -17,7 +17,7 @@ _start:
     mov [boot_params], rsi
 
     # Set CR3
-    mov rax, OFFSET LEVEL_4_TABLE
+    mov rax, OFFSET {level_4_table}
     mov cr3, rax
 
     lgdt [{gdt_ptr}] # Load the 64-bit global descriptor table.

src/arch/x86_64/platform/linux/mod.rs

@@ -28,6 +28,7 @@ mod entry {
 		loader_main = sym crate::os::loader_main,
 		stack = sym crate::arch::x86_64::stack::STACK,
 		stack_top_offset = const crate::arch::x86_64::stack::Stack::top_offset(),
+		level_4_table = sym crate::arch::x86_64::page_tables::LEVEL_4_TABLE,
 		gdt_ptr = sym crate::arch::x86_64::gdt::GDT_PTR,
 		kernel_code_selector = const crate::arch::x86_64::gdt::Gdt::kernel_code_selector().0,
 		kernel_data_selector = const crate::arch::x86_64::gdt::Gdt::kernel_data_selector().0,

src/arch/x86_64/platform/multiboot/entry.s

@@ -72,7 +72,7 @@ cpu_init:
     jz Linvalid # They aren't, there is no long mode.
 
     # Set CR3
-    mov eax, OFFSET LEVEL_4_TABLE
+    mov eax, OFFSET {level_4_table}
     mov cr3, eax
 
     # we need to enable PAE modus

src/arch/x86_64/platform/multiboot/mod.rs

@@ -29,6 +29,7 @@ mod entry {
 		loader_main = sym crate::os::loader_main,
 		stack = sym crate::arch::x86_64::stack::STACK,
 		stack_top_offset = const crate::arch::x86_64::stack::Stack::top_offset(),
+		level_4_table = sym crate::arch::x86_64::page_tables::LEVEL_4_TABLE,
 		gdt_ptr = sym crate::arch::x86_64::gdt::GDT_PTR,
 		kernel_code_selector = const crate::arch::x86_64::gdt::Gdt::kernel_code_selector().0,
 		kernel_data_selector = const crate::arch::x86_64::gdt::Gdt::kernel_data_selector().0,