[codegen 1.5] Port & convert module signature generation to a pass

This pass runs on all blocks without signatures in a package and populates them. The latency calculation for pipelined blocks is simplified to use the schedule information, if present.

For signature preservation, we also update block cloning to clone the signature and initiation interval.

PiperOrigin-RevId: 853909739

Author: ericastor

xls/codegen/BUILD

@@ -602,6 +602,7 @@ cc_library(
         "//xls/ir:op",
         "//xls/ir:register",
         "//xls/ir:xls_ir_interface_cc_proto",
+        "@com_google_absl//absl/base:core_headers",
         "@com_google_absl//absl/container:flat_hash_map",
         "@com_google_absl//absl/log",
         "@com_google_absl//absl/log:check",

xls/codegen/codegen_options.h

@@ -22,6 +22,7 @@
 #include <utility>
 #include <vector>
 
+#include "absl/base/optimization.h"
 #include "absl/container/flat_hash_map.h"
 #include "absl/log/check.h"
 #include "absl/types/span.h"
@@ -58,14 +59,24 @@ class CodegenOptions {
   static int64_t IOKindLatency(IOKind kind) {
     switch (kind) {
       case IOKind::kFlop:
-        return 1;
       case IOKind::kSkidBuffer:
         return 1;
       case IOKind::kZeroLatencyBuffer:
         return 0;
-      default:
-        return 9999;
     }
+    ABSL_UNREACHABLE();
+  }
+
+  static int64_t FlopKindLatency(FlopKind kind) {
+    switch (kind) {
+      case FlopKind::kNone:
+      case FlopKind::kZeroLatency:
+        return 0;
+      case FlopKind::kFlop:
+      case FlopKind::kSkid:
+        return 1;
+    }
+    ABSL_UNREACHABLE();
   }
 
   // TODO(allight): Merge these two enums.

xls/codegen_v_1_5/BUILD

@@ -53,6 +53,7 @@ cc_library(
         ":scheduled_block_conversion_pass",
         ":scheduling_pass",
         ":side_effect_condition_pass",
+        ":signature_generation_pass",
         ":state_to_register_io_lowering_pass",
         "//xls/passes:dataflow_simplification_pass",
         "//xls/passes:dce_pass",
@@ -734,6 +735,63 @@ cc_test(
     ],
 )
 
+cc_library(
+    name = "signature_generation_pass",
+    srcs = ["signature_generation_pass.cc"],
+    hdrs = ["signature_generation_pass.h"],
+    deps = [
+        ":block_conversion_pass",
+        "//xls/codegen:codegen_options",
+        "//xls/codegen:module_signature",
+        "//xls/codegen:module_signature_cc_proto",
+        "//xls/codegen/vast",
+        "//xls/common:casts",
+        "//xls/common/logging:log_lines",
+        "//xls/common/status:ret_check",
+        "//xls/common/status:status_macros",
+        "//xls/ir",
+        "//xls/ir:channel",
+        "//xls/ir:channel_cc_proto",
+        "//xls/ir:type",
+        "//xls/passes:pass_base",
+        "@com_google_absl//absl/log",
+        "@com_google_absl//absl/log:check",
+        "@com_google_absl//absl/status:statusor",
+        "@com_google_absl//absl/strings:str_format",
+    ],
+)
+
+cc_test(
+    name = "signature_generation_pass_test",
+    srcs = ["signature_generation_pass_test.cc"],
+    deps = [
+        ":block_conversion_pass",
+        ":channel_to_port_io_lowering_pass",
+        ":function_io_lowering_pass",
+        ":scheduled_block_conversion_pass",
+        ":signature_generation_pass",
+        "//xls/codegen:codegen_options",
+        "//xls/codegen:module_signature",
+        "//xls/codegen:module_signature_cc_proto",
+        "//xls/common:proto_test_utils",
+        "//xls/common:xls_gunit_main",
+        "//xls/common/status:matchers",
+        "//xls/common/status:status_macros",
+        "//xls/ir",
+        "//xls/ir:channel",
+        "//xls/ir:channel_cc_proto",
+        "//xls/ir:channel_ops",
+        "//xls/ir:clone_package",
+        "//xls/ir:function_builder",
+        "//xls/ir:ir_parser",
+        "//xls/ir:ir_test_base",
+        "//xls/ir:type",
+        "//xls/passes:pass_base",
+        "@com_google_absl//absl/status:statusor",
+        "@googletest//:gtest",
+    ],
+)
+
 cc_test(
     name = "scheduled_block_conversion_pass_test",
     srcs = ["scheduled_block_conversion_pass_test.cc"],

xls/codegen_v_1_5/block_conversion_pass_pipeline.cc

@@ -32,6 +32,7 @@
 #include "xls/codegen_v_1_5/scheduled_block_conversion_pass.h"
 #include "xls/codegen_v_1_5/scheduling_pass.h"
 #include "xls/codegen_v_1_5/side_effect_condition_pass.h"
+#include "xls/codegen_v_1_5/signature_generation_pass.h"
 #include "xls/codegen_v_1_5/state_to_register_io_lowering_pass.h"
 #include "xls/passes/dataflow_simplification_pass.h"
 #include "xls/passes/dce_pass.h"
@@ -63,6 +64,9 @@ std::unique_ptr<BlockConversionCompoundPass> CreateBlockConversionPassPipeline(
   // Lower params and return values to ports.
   top->Add<FunctionIOLoweringPass>();
 
+  // Add module signatures.
+  top->Add<SignatureGenerationPass>();
+
   // Insert flow control between stages.
   top->Add<FlowControlInsertionPass>();
 

xls/codegen_v_1_5/block_conversion_pass_pipeline_test.cc

@@ -141,7 +141,7 @@ class BlockConversionTest : public BlockConversionTestFixture {
   }
 
   CodegenOptions codegen_options() {
-    return CodegenOptions().module_name(TestName());
+    return CodegenOptions().module_name(TestName()).clock_name("clk");
   }
 
   absl::StatusOr<Block*> ConvertToBlock(

xls/codegen_v_1_5/channel_to_port_io_lowering_pass.cc

@@ -266,6 +266,67 @@ GetLoopbackChannels(ScheduledBlock* block) {
   return loopback_channels;
 }
 
+FlopKind GetDefaultFlopKind(bool enabled,
+                            ::xls::verilog::CodegenOptions::IOKind kind) {
+  if (!enabled) {
+    return FlopKind::kNone;
+  }
+  return ::xls::verilog::CodegenOptions::IOKindToFlopKind(kind);
+}
+
+absl::StatusOr<FlopKind> GetFlopKind(
+    ChannelRef channel, ChannelDirection direction, ScheduledBlock* block,
+    const BlockConversionPassOptions& options) {
+  if (ChannelRefKind(channel) == ChannelKind::kSingleValue) {
+    // NOTE: We control the flop insertion for single-value channels globally,
+    // with no per-channel configuration. This matches the behavior in codegen
+    // v1.0.
+    if (!options.codegen_options.flop_single_value_channels()) {
+      return FlopKind::kNone;
+    }
+    switch (direction) {
+      case ChannelDirection::kSend: {
+        if (!options.codegen_options.flop_outputs()) {
+          return FlopKind::kNone;
+        }
+        return FlopKind::kFlop;
+      }
+      case ChannelDirection::kReceive: {
+        if (!options.codegen_options.flop_inputs()) {
+          return FlopKind::kNone;
+        }
+        return FlopKind::kFlop;
+      }
+    }
+    ABSL_UNREACHABLE();
+    return absl::InternalError(
+        absl::StrFormat("Unknown channel direction %d", direction));
+  }
+
+  if (std::holds_alternative<Channel*>(channel)) {
+    XLS_RET_CHECK(!block->package()->ChannelsAreProcScoped())
+        << "For proc-scoped channels, the flop kind is set on the interface.";
+    XLS_RET_CHECK_EQ(ChannelRefKind(channel), ChannelKind::kStreaming);
+    StreamingChannel* streaming_channel =
+        down_cast<StreamingChannel*>(std::get<Channel*>(channel));
+    switch (direction) {
+      case ChannelDirection::kSend:
+        return streaming_channel->channel_config().output_flop_kind().value_or(
+            GetDefaultFlopKind(options.codegen_options.flop_outputs(),
+                               options.codegen_options.flop_outputs_kind()));
+      case ChannelDirection::kReceive:
+        return streaming_channel->channel_config().input_flop_kind().value_or(
+            GetDefaultFlopKind(options.codegen_options.flop_inputs(),
+                               options.codegen_options.flop_inputs_kind()));
+    }
+    ABSL_UNREACHABLE();
+    return absl::InternalError(
+        absl::StrFormat("Unknown channel direction %d", direction));
+  } else {
+    return std::get<ChannelInterface*>(channel)->flop_kind();
+  }
+}
+
 absl::StatusOr<Connector> AddPortsForSend(
     ChannelRef channel, ScheduledBlock* block,
     const BlockConversionPassOptions& options) {
@@ -317,12 +378,15 @@ absl::StatusOr<Connector> AddPortsForSend(
                       .valid = valid,
                       .ready = ready};
 
+  XLS_ASSIGN_OR_RETURN(
+      FlopKind flop_kind,
+      GetFlopKind(channel, ChannelDirection::kSend, block, options));
   XLS_RETURN_IF_ERROR(block->AddChannelPortMetadata(
       ChannelPortMetadata{.channel_name = std::string(ChannelRefName(channel)),
                           .type = ChannelRefType(channel),
                           .direction = ChannelDirection::kSend,
                           .channel_kind = ChannelRefKind(channel),
-                          .flop_kind = FlopKind::kNone,
+                          .flop_kind = flop_kind,
                           .data_port = data->GetName(),
                           .valid_port = GetOptionalNodeName(valid),
                           .ready_port = GetOptionalNodeName(ready)}));
@@ -378,12 +442,15 @@ absl::StatusOr<Connector> AddPortsForReceive(
                       .valid = valid,
                       .ready = ready};
 
+  XLS_ASSIGN_OR_RETURN(
+      FlopKind flop_kind,
+      GetFlopKind(channel, ChannelDirection::kReceive, block, options));
   XLS_RETURN_IF_ERROR(block->AddChannelPortMetadata(
       ChannelPortMetadata{.channel_name = std::string(ChannelRefName(channel)),
                           .type = ChannelRefType(channel),
                           .direction = ChannelDirection::kReceive,
                           .channel_kind = ChannelRefKind(channel),
-                          .flop_kind = FlopKind::kNone,
+                          .flop_kind = flop_kind,
                           .data_port = data->GetName(),
                           .valid_port = GetOptionalNodeName(valid),
                           .ready_port = GetOptionalNodeName(ready)}));
@@ -1123,67 +1190,6 @@ absl::flat_hash_set<std::string> GetRamChannelNames(
   return ram_channel_names;
 }
 
-FlopKind GetDefaultFlopKind(bool enabled,
-                            ::xls::verilog::CodegenOptions::IOKind kind) {
-  if (!enabled) {
-    return FlopKind::kNone;
-  }
-  return ::xls::verilog::CodegenOptions::IOKindToFlopKind(kind);
-}
-
-absl::StatusOr<FlopKind> GetFlopKind(
-    ChannelRef channel, ChannelDirection direction, ScheduledBlock* block,
-    const BlockConversionPassOptions& options) {
-  if (ChannelRefKind(channel) == ChannelKind::kSingleValue) {
-    // NOTE: We control the flop insertion for single-value channels globally,
-    // with no per-channel configuration. This matches the behavior in codegen
-    // v1.0.
-    if (!options.codegen_options.flop_single_value_channels()) {
-      return FlopKind::kNone;
-    }
-    switch (direction) {
-      case ChannelDirection::kSend: {
-        if (!options.codegen_options.flop_outputs()) {
-          return FlopKind::kNone;
-        }
-        return FlopKind::kFlop;
-      }
-      case ChannelDirection::kReceive: {
-        if (!options.codegen_options.flop_inputs()) {
-          return FlopKind::kNone;
-        }
-        return FlopKind::kFlop;
-      }
-    }
-    ABSL_UNREACHABLE();
-    return absl::InternalError(
-        absl::StrFormat("Unknown channel direction %d", direction));
-  }
-
-  if (std::holds_alternative<Channel*>(channel)) {
-    XLS_RET_CHECK(!block->package()->ChannelsAreProcScoped())
-        << "For proc-scoped channels, the flop kind is set on the interface.";
-    XLS_RET_CHECK_EQ(ChannelRefKind(channel), ChannelKind::kStreaming);
-    StreamingChannel* streaming_channel =
-        down_cast<StreamingChannel*>(std::get<Channel*>(channel));
-    switch (direction) {
-      case ChannelDirection::kSend:
-        return streaming_channel->channel_config().output_flop_kind().value_or(
-            GetDefaultFlopKind(options.codegen_options.flop_outputs(),
-                               options.codegen_options.flop_outputs_kind()));
-      case ChannelDirection::kReceive:
-        return streaming_channel->channel_config().input_flop_kind().value_or(
-            GetDefaultFlopKind(options.codegen_options.flop_inputs(),
-                               options.codegen_options.flop_inputs_kind()));
-    }
-    ABSL_UNREACHABLE();
-    return absl::InternalError(
-        absl::StrFormat("Unknown channel direction %d", direction));
-  } else {
-    return std::get<ChannelInterface*>(channel)->flop_kind();
-  }
-}
-
 // Adds a register between the node and all its downstream users.
 // Returns the new register added.
 absl::StatusOr<RegisterRead*> AddRegisterAfterNode(

xls/codegen_v_1_5/side_effect_condition_pass_test.cc

@@ -121,7 +121,10 @@ class SideEffectConditionPassTest
 
   static BlockConversionPassOptions CreateBlockConversionPassOptions(
       ::xls::verilog::CodegenOptions codegen_options =
-          ::xls::verilog::CodegenOptions().clock_name("clk")) {
+          ::xls::verilog::CodegenOptions()) {
+    if (codegen_options.clock_name().value_or("").empty()) {
+      codegen_options.clock_name("clk");
+    }
     return BlockConversionPassOptions{
         .codegen_options = std::move(codegen_options),
         .package_schedule = {},