Instructions in README

[Logimancer]

Would it be possible to add a "How to install on board" section to the README? I have the Pynq and am unable to load your files via vivado 2019.2.

[keck9939]

I'll second this. This is an intriguing project, but it not obvious how to get started with it.

[keck9939]

After some experimentation I was able to build the bitstream as follows:

1. Clone the repo. Make sure the top level directory is all lower case ("socdp8").

2. Rename the file "socdp8/src/rtl/io/pt08.vhd" to "socdp8/src/rtl/io/asr33.vhd"

3. With your current directory in the same directory that contains socdp8 start Vivado.

4. In the Vivado Tcl console enter:

source ./socdp8/src/fpga/boards/pynq-z2-project.tcl

Let it grind away. Note that Vivado does not necessarily give any good indication of when it is done. I found it useful to monitor CPU utilization. When it drops to near 0 you can assume it is done.

5. If you are not using Vivado 2019.2, edit "socdp8\src\fpga\boards\blockdesign\pynq_z2_block.tcl" to reflect the version you are using. Note this is not sure to work, but I was able to build with 2022.1.

6. In the Vivado Tcl console enter:

source ./socdp8/src/fpga/boards/blockdesign/pynq_z2_block.tcl

Let it grind away again.

6. When you are sure it is done, in the Hierarchy Sources window, right click on the pynq_z2_block_i item (yellow icons) and choose "Create HDL wrapper..." and use the default.

7. Right click on the generated wrapper in the Hierarchy Sources window, and choose "Set as top"

You should now be able to "Generate Bitstream".

I did this using Vivado in WSL on Windows. I expect it will work on Linux and probably native on Windows as well.

Now on to figuring out how to do the yocto build.