Net types not explicitly declared, but default_nettyp set to none

[heavySea]

With 08cd6eb and 581068f the compiler directive ``default_nettype none` was introduced to some (not all) files, including all testbench files.
The directive requires that the type of nets of all ports in the modules must be defined.

The design of the management soc uses implicit port type declarations most of the time. Moreover the produced netlists from yosys do not include port type declarations!

Using any other simulator than Icarus Verilog, above described problem will result in "missing net type declarations" errors.

This problem is closely related to the google/skywater-pdk#198, where the use of implicit net type declarations was already discussed but without a resolution.

Due to the use of implicit declarations everywhere, I would suggest to remove the compiler directive ``default_nettype none`.

[WallieEverest]

If we could get the PDK libraries to explicitly declare wires, then this discussion would be resolved.
For example:
change output Y;
to output wire Y;

Better yet, just migrate to the Verilog 2001 convention of fully qualified port names.