64 bit CPU takes misaligned exception in mtvec_handler ?

[algrobman]

trying to simulate simple arithmetic test: riscv_arithmetic_basic_test_0.S.

the cpu takes misaligned store exception here:

mtvec_handler:    
                  addi x17, x17, -4  <<<  why is it 4 ?
                  sd  x22, (x17)  <<<< exception

Is there any control to avoid it?

[algrobman]

BTW,
why do the handlers save/restore all GPRs while only a few are used /changed in the handlers?

[dpetrisko]

Related to #925 ?

[algrobman]

yes, it is. BTW, does somebody maintain this repo? Why isn't this fixed in master/latest?

[algrobman]

@dpetrisko , thanks for pointing the fix