No way to generate VCD files

[slavishayov]

The chisel-template compile and emits SystemVerilog as expected. The only problem is to generated the vcd (or fst) files. I read that this is automatically done but the vcd file is not generated.
I found that there's a function emitVcd but don't know where to apply it.
Any help would be appreciated.
Thanks

[seldridge]

I can't recall the exact invocation to do this with sbt, but with mill you can just add -DemitVcd=1. What is going on here is that ChiselSim hooks into Scalatest's rudimentary command line option parsing. We have an option registered for emitting VCD files. The following is what I'm seeing when I run this:

# ./mill 'Foo.test' -DemitVcd=1 
[120/120] Foo.test.test
[120] GCDSpec:
[120] - Gcd should calculate proper greatest common denominator
[120] Run completed in 3 seconds, 3 milliseconds.
[120] Total number of tests run: 1
[120] Suites: completed 1, aborted 0
[120] Tests: succeeded 1, failed 0, canceled 0, ignored 0, pending 0
[120] All tests passed.
[120/120] ============================== Foo.test -DemitVcd=1 ============================== 3s                                                            
# find build -type f -name '*.vcd'
build/chiselsim/GCDSpec/Gcd-should-calculate-proper-greatest-common-denominator/workdir-verilator/trace.vcd

There aren't really any other options, but you can dump help text, too:

# ./mill 'Foo.test' -Dhelp=1      
[120/120] Foo.test.test
[120] GCDSpec:
[120] - Gcd should calculate proper greatest common denominator *** FAILED ***
[120]   chisel3.simulator.scalatest.HasCliOptions$$anon$5: help text requested
[120] ------------------------------------------------------------------------------
[120] Usage: <ScalaTest> [-D<name>=<value>...]
[120] 
[120] This ChiselSim ScalaTest test supports passing command line arguments via
[120] ScalaTest's "config map" feature.  To access this, append `-D<name>=<value>` for
[120] a legal option listed below.
[120] 
[120] Options:
[120] 
[120]   chiselOpts
[120]       additional options to pass to the Chisel elaboration
[120]   emitVcd
[120]       compile with VCD waveform support and start dumping waves at time zero
[120]   firtoolOpts
[120]       additional options to pass to the firtool compiler
[120]   help
[120]       display this help text
[120] 
[120] ------------------------------------------------------------------------------
[120]   ...
[120] Run completed in 167 milliseconds.
[120] Total number of tests run: 1
[120] Suites: completed 1, aborted 0
[120] Tests: succeeded 0, failed 1, canceled 0, ignored 0, pending 0
[120] *** 1 TEST FAILED ***

You should be able to do this with sbt for whatever the correct invocation is to get the options to Scalatest.

Edit: there's some documentation about how all this fits together here: https://www.chisel-lang.org/docs/explanations/testing#command-line-arguments

[slavishayov]

Dear @seldridge,
thank you very much for your reply.
I haven't tried on my side with mill.
I switched to mill and it does well accept the DemitVcd=1 argument! I obtain as expected the vcd trace.
Thank you very much for your help.
Slav

[seldridge]

Glad to know it worked!

[Jac0912]

The mill version of 'chisel-template' is too old. So I update to mill 1.1.0. But add -DemitVcd=1 didn't work for this config.
mill version: 1.1.0
chisel version: 7.7.0

import mill.*
import mill.scalalib.*

object foo extends ScalaModule {
  def scalaVersion = "2.13.18"

  // You can have arbitrary numbers of third-party dependencies
  def mvnDeps: T[Seq[Dep]] = super.mvnDeps() ++ Seq(
    mvn"org.chipsalliance::chisel:7.7.0",
    mvn"org.scalatest::scalatest::3.2.19"
  )

  override def scalacPluginMvnDeps: T[Seq[Dep]] = super.mvnDeps() ++ Seq(
    mvn"org.chipsalliance:::chisel-plugin:7.7.0",
  )

  object test extends ScalaTests {
    def testFramework = "org.scalatest.tools.Framework"

    override def scalacPluginMvnDeps: T[Seq[Dep]] = super.mvnDeps() ++ Seq(
      mvn"org.chipsalliance:::chisel-plugin:7.7.0"
    )

    def mvnDeps: T[Seq[Dep]] = super.mvnDeps() ++ Seq(
      mvn"org.scalatest::scalatest::3.2.19"
    )
  }

  // Choose a main class to use for `.run` if there are multiple present
  //  def mainClass: T[Option[String]] = Some("Main")

  def scalacOptions: T[Seq[String]] = Seq(
    "-language:reflectiveCalls",
    "-deprecation",
    "-feature",
    "-Xcheckinit",
    "-Ymacro-annotations",

  )
}

Here are some error:

131] - should FSM test *** FAILED ***
131]   svsim.Simulation$Message$Error: Cannot enable traces as simulator was not compiled to support them
131]   at svsim.Simulation$Controller.readNextAvailableMessage(Simulation.scala:185)
131]   at svsim.Simulation$Controller.$anonfun$completeInFlightCommands$1(Simulation.scala:225)
131]   at svsim.Simulation$Controller.$anonfun$completeInFlightCommands$1$adapted(Simulation.scala:224)
131]   at scala.collection.IterableOnceOps.foreach(IterableOnce.scala:630)
131]   at scala.collection.IterableOnceOps.foreach$(IterableOnce.scala:628)
131]   at scala.collection.AbstractIterable.foreach(Iterable.scala:936)
131]   at svsim.Simulation$Controller.completeInFlightCommands(Simulation.scala:224)
131]   at svsim.Simulation$Controller.processNextMessage(Simulation.scala:236)
131]   at svsim.Simulation$Port.tick(Simulation.scala:435)
131]   at chisel3.simulator.PeekPokeAPI$TestableClock.step(PeekPokeAPI.scala:304)
131]   ...