Description
Transistor gates don't respect spacing to the diffusion of a wider transistor next to them (this is a regression).
Steps to Reproduce
$ lm -p -c cells build --no-cells sky130_fd_sc_hd__dlrtp_1.spi
Expected Behavior
The poly gates should be offset from the diffusion to the left and right.
Versions
- OS: Ubuntu 24.04.1 LTS
- Loom Version: v0.12.2
Supporting Files and Screenshots
sky130_fd_sc_hd__dlrtp_1.spi
.subckt sky130_fd_sc_hd__dlrtp_1 D GATE RESET_B VGND VNB VPB VPWR Q
X0 VPWR a_560_425_2 a_711_21_2 VPB sky130_fd_pr__pfet_01v8_hvt w=1e+06u l=150000u
X1 a_711_21_2 a_560_425_2 a_929_47_2 VNB sky130_fd_pr__nfet_01v8 w=650000u l=150000u
X2 a_711_21_2 RESET_B VPWR VPB sky130_fd_pr__pfet_01v8_hvt w=1e+06u l=150000u
X3 VPWR a_299_47_2 a_465_369_2 VPB sky130_fd_pr__pfet_01v8_hvt w=640000u l=150000u
X4 a_299_47_2 D VPWR VPB sky130_fd_pr__pfet_01v8_hvt w=640000u l=150000u
X5 a_654_47_2 a_711_21_2 VGND VNB sky130_fd_pr__nfet_01v8 w=420000u l=150000u
X6 VPWR a_711_21_2 Q VPB sky130_fd_pr__pfet_01v8_hvt w=1e+06u l=150000u
X7 a_465_369_2 a_27_47_2 a_560_425_2 VPB sky130_fd_pr__pfet_01v8_hvt w=360000u l=150000u
X8 a_465_47_2 a_193_47_2 a_560_425_2 VNB sky130_fd_pr__nfet_01v8 w=420000u l=150000u
X9 a_560_425_2 a_27_47_2 a_654_47_2 VNB sky130_fd_pr__nfet_01v8 w=420000u l=150000u
X10 a_664_425_2 a_711_21_2 VPWR VPB sky130_fd_pr__pfet_01v8_hvt w=420000u l=150000u
X11 VGND a_299_47_2 a_465_47_2 VNB sky130_fd_pr__nfet_01v8 w=420000u l=150000u
X12 VGND a_27_47_2 a_193_47_2 VNB sky130_fd_pr__nfet_01v8 w=420000u l=150000u
X13 a_27_47_2 GATE VGND VNB sky130_fd_pr__nfet_01v8 w=420000u l=150000u
X14 a_27_47_2 GATE VPWR VPB sky130_fd_pr__pfet_01v8_hvt w=640000u l=150000u
X15 VGND a_711_21_2 Q VNB sky130_fd_pr__nfet_01v8 w=650000u l=150000u
X16 VPWR a_27_47_2 a_193_47_2 VPB sky130_fd_pr__pfet_01v8_hvt w=640000u l=150000u
X17 a_560_425_2 a_193_47_2 a_664_425_2 VPB sky130_fd_pr__pfet_01v8_hvt w=360000u l=150000u
X18 a_299_47_2 D VGND VNB sky130_fd_pr__nfet_01v8 w=420000u l=150000u
X19 a_929_47_2 RESET_B VGND VNB sky130_fd_pr__nfet_01v8 w=650000u l=150000u
.ends

Description
Transistor gates don't respect spacing to the diffusion of a wider transistor next to them (this is a regression).
Steps to Reproduce
Expected Behavior
The poly gates should be offset from the diffusion to the left and right.
Versions
Supporting Files and Screenshots
sky130_fd_sc_hd__dlrtp_1.spi