Add VHDL support

[alaindargelas]

Reuse an existing Antlr VHDL grammar,
Reuse the Surelog AST Serialization mechanism,
Model VHDL in the UHDM Data Model (Using the standard VHDL datagrams)
Write the VHDL Compilation into UHDM
Mingle the VHDL elaboration into the SystemVerilog elaboration code