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Copy file name to clipboardExpand all lines: LIMITATIONS.md
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# Scope and Model Architecture
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Aethermor is a **production thermal engineering toolkit** for chip thermal
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analysis, cooling tradeoffs, and compute-density optimization. This document
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describes what the project provides, the physics it models, and its
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analysis, cooling tradeoffs, and compute-density optimization.
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> **Scope: Production-stable for architecture-stage thermal exploration and inverse design; not intended for sign-off, transient package verification, or transistor-level thermal closure.**
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This document describes what the project provides, the physics it models, and its
Copy file name to clipboardExpand all lines: NVIDIA_ENGINEERING_BRIEF.md
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design space *before* committing to a detailed simulation — so your ANSYS runs
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confirm rather than surprise.
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> **Scope: Production-stable for architecture-stage thermal exploration and inverse design; not intended for sign-off, transient package verification, or transistor-level thermal closure.**
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**Note:** HotSpot (open-source, UVA) also provides fast thermal simulation with
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compact-model accuracy. Its HotFloorplan module supports layout-level
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optimization. Where Aethermor adds value is in substrate-aware inverse design
Copy file name to clipboardExpand all lines: README.md
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Handbook, ITRS/IRDS roadmaps, published specifications for real chips
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(NVIDIA A100, Apple M1, AMD EPYC, Intel i9-13900K), and published hardware
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measurements (JEDEC θ_jc thermal resistance, IR thermal imaging, HotSpot
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benchmarks). Aethermor is **production-ready** for architecture-stage
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thermal engineering — design-space exploration, material comparison,
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cooling-strategy tradeoffs, and compute-density optimization.
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benchmarks). **Scope: Production-stable for architecture-stage thermal exploration and inverse design; not intended for sign-off, transient package verification, or transistor-level thermal closure.**
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See [LIMITATIONS.md](LIMITATIONS.md) for scope and validation status.
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---
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- Published JEDEC-standard thermal resistance measurements and IR thermal imaging data
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- HotSpot simulation benchmarks
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Aethermor is **production-ready** for architecture-stage thermal engineering:
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design-space exploration, material comparison, cooling-strategy tradeoffs.
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**Scope: Production-stable for architecture-stage thermal exploration and inverse design; not intended for sign-off, transient package verification, or transistor-level thermal closure.**
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Detailed die-level correlation with proprietary floorplan data is a
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planned next step.
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| Document | What It Covers |
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|----------|---------------|
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|[docs/CASE_STUDY.md](docs/CASE_STUDY.md)| Decision-changing case study: cooling vs substrate vs redistribution |
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|[docs/CASE_STUDY.md](docs/CASE_STUDY.md)| Case study: cooling vs substrate vs redistribution |
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|[docs/CASE_STUDY_SOC.md](docs/CASE_STUDY_SOC.md)| Case study: SoC bottleneck reallocation (47% throughput for free) |
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|[docs/CASE_STUDY_PARADIGM.md](docs/CASE_STUDY_PARADIGM.md)| Case study: material + paradigm selection (SiC 232%, diamond 1387%) |
Copy file name to clipboardExpand all lines: RELEASE_NOTES_v1.0.0.md
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## What's New in 1.0.0
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Aethermor v1.0.0 upgrades the project from Beta to **Production/Stable** for
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architecture-stage thermal engineering. The key addition is experimental
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measurement validation — closing the gap between "matches published specs" and
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"matches real hardware measurements."
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Aethermor v1.0.0 upgrades the project from Beta to **Production/Stable**.
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> **Scope: Production-stable for architecture-stage thermal exploration and inverse design; not intended for sign-off, transient package verification, or transistor-level thermal closure.**
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The key addition is experimental measurement validation — closing the gap between
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"matches published specs" and "matches real hardware measurements."
Copy file name to clipboardExpand all lines: VALIDATION.md
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# Aethermor Validation Report
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> **Scope: Production-stable for architecture-stage thermal exploration and inverse design; not intended for sign-off, transient package verification, or transistor-level thermal closure.**
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